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1. (Digital Presentation) Multimodal Encapsulation of p-SnOx to Engineer the Carrier Density for Thin Film Transistor Applications

   https://doi.org/10.1149/MA2022-0215821mtgabs  

   Lee, Dong Hun ; Zhang, Yuxuan ; No, Kwangsoo ; Song, Han Wook ; Lee, Sunghwan ( October 2022 , ECS Meeting Abstracts)

   It has been challenging to synthesize p-type SnO_x(1≤x<2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band.

   We recently reported on the processing of p-type SnOx and an oxide-based p-n heterostructures, demonstrating high on/off rectification ratio (>10³), small turn-on voltage (<0.5 V), and low saturation current (~1×10^-10A)¹. In order to further understand the p-type oxide and engineer the properties for various electronic device applications, it is important to identify (or establish) the dominating doping and transport mechanisms. The low dopability in p-type SnOx, of which the causation is also closely related to the narrow processing window, needs to be mitigated so that the electrical properties of the material are to be adequately engineered^{2, 3}.

   Herein, we report on the multifunctional encapsulation of p-SnO_xto limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnO_xchannel for thin film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry measurements identified that ultra-thin SiO₂as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnO_xand augmented hydrogen density across the entire thickness of the channel. Encapsulated p-SnO_x-based TFTs demonstrated much-enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current. The relevance between the TFT performance and the effects of oxygen suppression and hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. These results are supported by density-functional-theory calculations.

   Acknowledgement

   This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education.

   References

   Lee, D. H.; Park, H.; Clevenger, M.; Kim, H.; Kim, C. S.; Liu, M.; Kim, G.; Song, H. W.; No, K.; Kim, S. Y.; Ko, D.-K.; Lucietto, A.; Park, H.; Lee, S., High-Performance Oxide-Based p–n Heterojunctions Integrating p-SnOx and n-InGaZnO.ACS Applied Materials & Interfaces2021,13(46), 55676-55686.

   Hautier, G.; Miglio, A.; Ceder, G.; Rignanese, G.-M.; Gonze, X., Identification and design principles of low hole effective mass p-type transparent conducting oxides.Nat Commun2013,4.

   Yim, K.; Youn, Y.; Lee, M.; Yoo, D.; Lee, J.; Cho, S. H.; Han, S., Computational discovery of p-type transparent oxide semiconductors using hydrogen descriptor.npj Computational Materials2018,4(1), 17.

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2. Mitigating Heavy Ion Irradiation‐Induced Degradation in p‐type SnO Thin‐Film Transistors at Room Temperature

   https://doi.org/10.1002/pssa.202300392  

   Al-Mamun, Nahid Sultan ; Rasel, Md Abu Jafar ; Wolfe, Douglas E. ; Haque, Aman ; Schoell, Ryan ; Hattar, Khalid ; Ryu, Seung Ho ; Kim, Seong Keun ( September 2023 , physica status solidi (a))

   The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au⁴⁺irradiation at a fluence level of 5.2 × 10¹² ions cm⁻², the output drain current and on/off current ratio (I_on/I_off) decrease by more than one order of magnitude, field‐effect mobility (μ_FE) reduces more than four times, and subthreshold swing (SS) increases more than four times along with a negative shift in threshold voltage. The observed degradation is attributed to increased surface roughness and defect density, as confirmed by scanning electron microscopy (SEM), high‐resolution micro‐Raman, and transmission electron microscopy (TEM) with geometric phase analysis (GPA). A technique is demonstrated to recover the device performance at room temperature and in less than a minute, using the electron wind force (EWF) obtained from low‐duty‐cycle high‐density pulsed current. At a pulsed current density of 4.0 × 10⁵ A cm⁻², approximately four times increase inI_on/I_offis observed, 41% increase inμ_FE, and 20% decrease in the SS of the irradiated TFTs, suggesting effectiveness of the new annealing technique.

    

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3. Strategies to Enhance the Capability of Carrier Injection to the Effective Channel for Bottom-gated Amorphous Oxide Thin Films Transistors

   Liu, Mingyuan ; Kim, Hyeonghun ; Song, Han Wook ; Lee, Sunghwan ( November 2021 , Materials Research Society)

   Over the two decades, amorphous oxide semiconductors (AOSs) and their thin film transistor (TFT) channel application have been intensely explored to realize high performance, transparent and flexible displays due to their high field effect mobility (μFE=5-20 cm2/Vs), visible range optical transparency, and low temperature processability (25-300 °C).[1-2] The metastable amorphous phase is to be maintained during operation by the addition of Zn and additional third cation species (e.g., Ga, Hf, or Al) as an amorphous phase stabilizer.[3-5] To limit TFT off-state currents, a thin channel layer (10-20 nm) was employed for InZnO (IZO)-based TFTs, or third cations were added to suppress carrier generations in the TFT channel. To resolve bias stress-induced instabilities in TFT performance, approaches to employ defect passivation layers or enhance channel/dielectric interfacial compatibility were demonstrated.[6-7] Metallization contact is also a dominating factor that determines the performance of TFTs. Particularly, it has been reported that high electrical contact resistance significantly sacrifices drain bias applied to the channel, which leads to undesirable power loss during TFT operation and issues for the measurement of TFT field effect mobilities. [2, 8] However, only a few reports that suggest strategies to enhance contact behaviors are available in the literature. Furthermore, the previous approaches (1) require an additional fabrication complexity due to the use of additional treatments at relatively harsh conditions such as UV, plasma, or high temperatures, and (2) may lead to adverse effects on the channel material attributed to the chemical incompatibility between dissimilar materials, and exposures to harsh environments. Therefore, a simple and easy but effective buffer strategy, which does not require any additional process complexities and not sacrifice chemical compatibility, needs to be established to mitigate the contact issues and therefore achieve high performance and low power consumption AOS TFTs. The present study aims to demonstrate an approach utilizing an interfacial buffer layer, which is compositionally homogeneous to the channel to better align work functions between channel and metallization without a significant fabrication complexity and harsh treatment conditions. Photoelectron spectroscopic measurements reveal that the conducting IZO buffer, of which the work function (Φ) is 4.37 eV, relaxes a relatively large Φ difference between channel IZO (Φ=4.81 eV) and Ti (Φ=4.2-4.3 eV) metallization. The buffer is found to lower the energy barrier for charge carriers at the source to reach the effective channel region near the dielectric. In addition, the higher carrier density of the buffer and favorable chemical compatibility with the channel (compositionally the same) further contribute to a significant reduction in specific contact resistance as much as more than 2.5 orders of magnitude. The improved contact and carrier supply performance from the source to the channel lead to an enhanced field effect mobility of up to 56.49 cm2/Vs and a threshold voltage of 1.18 V, compared to 13.41 cm2/Vs and 7.44 V of IZO TFTs without a buffer. The present work is unique in that an approach to lower the potential barrier between the source and the effective channel region (located near the channel/dielectric interface, behaving similar to a buried-channel MOSFET [9]) by introducing a contact buffer layer that enhances the field effect mobility and facilitates carrier supply from the source to the effective channel region. 

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4. Stable Universal 1‐ and 2‐Input Single‐Molecule Logic Gates

   https://doi.org/10.1002/adma.202202135  

   Liu, Ran ; Han, Yingmei ; Sun, Feng ; Khatri, Gyan ; Kwon, Jaesuk ; Nickle, Cameron ; Wang, Lejia ; Wang, Chuan‐Kui ; Thompson, Damien ; Li, Zong‐Liang ; et al ( May 2022 , Advanced Materials)

   Controllable single‐molecule logic operations will enable development of reliable ultra‐minimalistic circuit elements for high‐density computing but require stable currents from multiple orthogonal inputs in molecular junctions. Utilizing the two unique adjacent conductive molecular orbitals (MOs) of gated Au/S‐(CH₂)₃‐Fc‐(CH₂)₉‐S/Au (Fc = ferrocene) single‐electron transistors (≈2 nm), a stable single‐electron logic calculator (SELC) is presented, which allows real‐time modulation of output current as a function of orthogonal input bias (V_b) and gate (V_g) voltages. Reliable and low‐voltage (ǀV_bǀ ≤ 80 mV, ǀV_gǀ ≤ 2 V) operations of the SELC depend upon the unambiguous association of current resonances with energy shifts of the MOs (which show an invariable, small energy separation of ≈100 meV) in response to the changes of voltages, which is confirmed by electron‐transport calculations. Stable multi‐logic operations based on the SELC modulated current conversions between the two resonances and Coulomb blockade regimes are demonstrated via the implementation of all universal 1‐input (YES/NOT/PASS_1/PASS_0) and 2‐input (AND/XOR/OR/NAND/NOR/INT/XNOR) logic gates.

    

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5. High‐Performance Zinc Tin Oxide TFTs with Active Layers Deposited by Atomic Layer Deposition

   https://doi.org/10.1002/aelm.202000195  

   Allemang, Christopher R. ; Cho, Tae H. ; Trejo, Orlando ; Ravan, Shantam ; Rodríguez, Robin E. ; Dasgupta, Neil P. ; Peterson, Rebecca L. ( June 2020 , Advanced Electronic Materials)

   New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm²V⁻¹s⁻¹, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm²V^–1s^–1and a subthreshold slope of 0.29 V dec^–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐kgate insulator (ALD Al₂O₃), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates.

    

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