Defect mitigation of electronic devices is conventionally achieved using thermal annealing. To mobilize the defects, very high temperatures are necessary. Since thermal diffusion is random in nature, the process may take a prolonged period of time. In contrast, we demonstrate a room temperature annealing technique that takes only a few seconds. The fundamental mechanism is defect mobilization by atomic scale mechanical force originating from very high current density but low duty cycle electrical pulses. The high-energy electrons lose their momentum upon collision with the defects, yet the low duty cycle suppresses any heat accumulation to keep the temperature ambient. For a 7 × 105A cm−2pulsed current, we report an approximately 26% reduction in specific on-resistance, a 50% increase of the rectification ratio with a lower ideality factor, and reverse leakage current for as-fabricated vertical geometry GaN p–n diodes. We characterize the microscopic defect density of the devices before and after the room temperature processing to explain the improvement in the electrical characteristics. Raman analysis reveals an improvement in the crystallinity of the GaN layer and an approximately 40% relaxation of any post-fabrication residual strain compared to the as-received sample. Cross-sectional transmission electron microscopy (TEM) images and geometric phase analysis results of high-resolution TEM images further confirm the effectiveness of the proposed room temperature annealing technique to mitigate defects in the device. No detrimental effect, such as diffusion and/or segregation of elements, is observed as a result of applying a high-density pulsed current, as confirmed by energy dispersive x-ray spectroscopy mapping.
The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au4+irradiation at a fluence level of 5.2 × 1012 ions cm−2, the output drain current and on/off current ratio (
- NSF-PAR ID:
- 10468090
- Publisher / Repository:
- Wiley Blackwell (John Wiley & Sons)
- Date Published:
- Journal Name:
- physica status solidi (a)
- Volume:
- 220
- Issue:
- 19
- ISSN:
- 1862-6300
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Abstract The prospect of 2‐dimensional electron gases (2DEGs) possessing high mobility at room temperature in wide‐bandgap perovskite stannates is enticing for oxide electronics, particularly to realize transparent and high‐electron mobility transistors. Nonetheless only a small number of studies to date report 2DEGs in BaSnO3‐based heterostructures. Here, 2DEG formation at the LaScO3/BaSnO3(LSO/BSO) interface with a room‐temperature mobility of 60 cm2 V−1 s−1at a carrier concentration of 1.7 × 1013 cm–2is reported. This is an order of magnitude higher mobility at room temperature than achieved in SrTiO3‐based 2DEGs. This is achieved by combining a thick BSO buffer layer with an ex situ high‐temperature treatment, which not only reduces the dislocation density but also produces a SnO2‐terminated atomically flat surface, followed by the growth of an overlying BSO/LSO interface. Using weak beam dark‐field transmission electron microscopy imaging and in‐line electron holography technique, a reduction of the threading dislocation density is revealed, and direct evidence for the spatial confinement of a 2DEG at the BSO/LSO interface is provided. This work opens a new pathway to explore the exciting physics of stannate‐based 2DEGs at application‐relevant temperatures for oxide nanoelectronics.
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It has been challenging to synthesize p-type SnOx(1≤x<2) and engineer the electrical properties such as carrier density and mobility due to the narrow processing window and the localized oxygen 2p orbitals near the valence band.
We recently reported on the processing of p-type SnOx and an oxide-based p-n heterostructures, demonstrating high on/off rectification ratio (>103), small turn-on voltage (<0.5 V), and low saturation current (~1×10-10A)1. In order to further understand the p-type oxide and engineer the properties for various electronic device applications, it is important to identify (or establish) the dominating doping and transport mechanisms. The low dopability in p-type SnOx, of which the causation is also closely related to the narrow processing window, needs to be mitigated so that the electrical properties of the material are to be adequately engineered2, 3.
Herein, we report on the multifunctional encapsulation of p-SnOxto limit the surface adsorption of oxygen and selectively permeate hydrogen into the p-SnOxchannel for thin film transistor (TFT) applications. Time-of-flight secondary ion mass spectrometry measurements identified that ultra-thin SiO2as a multifunctional encapsulation layer effectively suppressed the oxygen adsorption on the back channel surface of p-SnOxand augmented hydrogen density across the entire thickness of the channel. Encapsulated p-SnOx-based TFTs demonstrated much-enhanced channel conductance modulation in response to the gate bias applied, featuring higher on-state current and lower off-state current. The relevance between the TFT performance and the effects of oxygen suppression and hydrogen permeation is discussed in regard to the intrinsic and extrinsic doping mechanisms. These results are supported by density-functional-theory calculations.
Acknowledgement This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS. K.N. was supported by Basic Science Research Program (NRF-2021R11A1A01051246) through the NRF Korea funded by the Ministry of Education.
References Lee, D. H.; Park, H.; Clevenger, M.; Kim, H.; Kim, C. S.; Liu, M.; Kim, G.; Song, H. W.; No, K.; Kim, S. Y.; Ko, D.-K.; Lucietto, A.; Park, H.; Lee, S., High-Performance Oxide-Based p–n Heterojunctions Integrating p-SnOx and n-InGaZnO.
ACS Applied Materials & Interfaces 2021, 13 (46), 55676-55686.Hautier, G.; Miglio, A.; Ceder, G.; Rignanese, G.-M.; Gonze, X., Identification and design principles of low hole effective mass p-type transparent conducting oxides.
Nat Commun 2013, 4 .Yim, K.; Youn, Y.; Lee, M.; Yoo, D.; Lee, J.; Cho, S. H.; Han, S., Computational discovery of p-type transparent oxide semiconductors using hydrogen descriptor.
npj Computational Materials 2018, 4 (1), 17.Figure 1
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Abstract Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS2, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe2transistors with impressive subthreshold slope (109 mV dec−1) and
I ON/I OFF(106) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe2in situ before metallization, which minimizes subsequent reactions between Sc and WSe2. Post metallization anneals in reducing environments (UHV, forming gas) degrade theI ON/I OFFby ~103and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe2, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe2layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe2Fermi level around individual Sc atoms in the WSe2lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe2transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe2. -
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Additive patterning of transparent conducting metal oxides at low temperatures is a critical step in realizing low‐cost transparent electronics for display technology and photovoltaics. In this work, inkjet‐printed metal oxide transistors based on pure aqueous chemistries are presented. These inks readily convert to functional thin films at lower processing temperatures (
T ≤ 250 °C) relative to organic solvent‐based oxide inks, facilitating the fabrication of high‐performance transistors with both inkjet‐printed transparent electrodes of aluminum‐doped cadmium oxide (ACO) and semiconductor (InOx ). The intrinsic fluid properties of these water‐based solutions enable the printing of fine features with coffee‐ring free line profiles and smoother line edges than those formed from organic solvent‐based inks. The influence of low‐temperature annealing on the optical, electrical, and crystallographic properties of the ACO electrodes is investigated, as well as the role of aluminum doping in improving these properties. Finally, the all‐aqueous‐printed thin film transistors (TFTs) with inkjet‐patterned semiconductor (InOx ) and source/drain (ACO) layers are characterized, which show ideal low contact resistance (R c< 160 Ω cm) and competitive transistor performance (µ linup to 19 cm2V−1s−1, Subthreshold Slope (SS) ≤150 mV dec−1) with only low‐temperature processing (T ≤ 250 °C).
