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1. ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models

   https://doi.org/10.1145/3676536.3676816  

   Yin, Yuxuan; Wang, Yu; Xu, Boxun; Li, Peng (October 2024, 2024 ACM/IEEE International Conference on Computer-Aided Design)

   Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO's inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO's probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO's exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness. 

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2. CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing

   https://doi.org/10.1145/3380446.3430633  

   Wu, Zhengfeng; Savidis, Ioannis (November 2020, Proceedings of the ACM/IEEE Workshop on Machine Learning for Computer Aided Design (MLCAD))

   null (Ed.)

   A novel simulation-based framework that applies classification with adaptive labeling thresholds (CALT) is developed that auto-generates the component sizes of an analog integrated circuit. Classifiers are applied to predict whether the target specifications are satisfied. To address the lack of data points with positive labels due to the large dimensionality of the parameter space, the labeling threshold is adaptively set to a certain percentile of the distribution of a given circuit performance metric in the dataset. Random forest classifiers are executed for surrogate prediction modeling that provide a ranking of the design parameters. For each iteration of the simulation loop, optimization is utilized to determine new query points. CALT is applied to the design of a low noise amplifier (LNA) in a 65 nm technology. Qualified design solutions are generated for two sets of specifications with an average execution of 4 and 17 iterations of the optimization loop, which require an average of 1287 and 2190 simulation samples, and an average execution time of 5.4 hours and 23.2 hours, respectively. CALT is a specification-driven design framework to automate the sizing of the components (transistors, capacitors, inductors, etc.) of an analog circuit. CALT generates interpretable models and achieves high sample efficiency without requiring the use of prior circuit models. 

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3. Pareto Optimization of Analog circuits using Reinforcement Learning

   https://doi.org/10.1145/3640463  

   NS, Karthik Somayaji; Li, Peng (January 2024, ACM Transactions on Design Automation of Electronic Systems)

   Analog circuit optimization and design presents a unique set of challenges in the IC design process. Many applications require for the designer to optimize for multiple competing objectives which poses a crucial challenge. Motivated by these practical aspects, we propose a novel method to tackle multi-objective optimization for analog circuit design in continuous action spaces. In particular, we propose to: (i) Extrapolate current techniques in Multi-Objective Reinforcement Learning (MORL) to continuous state and action spaces. (ii) Provide for a dynamically tunable trained model to query user defined preferences in multi-objective optimization in the analog circuit design context. 

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4. Security Vulnerabilities of Obfuscated Analog Circuits

   https://doi.org/10.1109/ISCAS45731.2020.9180781  

   Rao, Vaibhav Venugopal; Juretus, Kyle; Savidis, Ioannis (October 2020, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS))

   null (Ed.)

   Vulnerabilities of key based analog obfuscation methodologies that modify the transistor dimensions of a circuit are evaluated. Two attack vectors on a common source amplifier, differential amplifier, operational amplifier, and voltage controlled oscillator are developed. The first attack exploits the lack of possible key combinations permitted around the correct key, which is a result of requiring a unique key to lock the circuit. An average of 5 possible key combinations were returned in an average of 5.47 seconds when executing the key spacing attack. The second attack vector utilizes the monotonic relationship between the sizing of the transistors and the functional response of the circuit to determine the correct key. The average time to execute the attack, while assuming process, voltage, and temperature (PVT) variation of 10%, was 1.18 seconds. Both equal key spacing and non-monotonic key dependencies are discussed as ways to mitigate the threats to future analog obfuscation techniques. 

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5. Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits

   https://doi.org/10.1109/ITC44778.2020.9325209  

   Sanabria-Borbon, A.; Jayasankaran, N. G.; Lee, S.; Sanchez-Sinencio, E.; Hu, J.; Rajendran, J. (November 2020, IEEE International Test Conference)

   null (Ed.)

   Analog/RF performance locking techniques insert configurable components to obfuscate the biasing or the design parameters of the secured analog block. The locked circuit meets the specifications only under a specific configuration decided by the correct common key, shared by all chip instances of the same design. Key provisioning enables the design of distinct user keys for individual chip instances. This area has received little research attention, and a naive approach yields large area overhead when increasing the key size. We propose a new approach based on a Schmitt trigger (ST) circuit with configurable hysteresis. The proposed key provisioning is compatible with existing analog locking techniques and has a constant area overhead regardless of key size. This approach is tested with three analog/RF circuits to demonstrate its area scalability and effectiveness on security. 

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