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Title: Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography
Ring-Binary-Learning-with-Errors (RBLWE)-based post-quantum cryptography (PQC) is a promising scheme suitable for lightweight applications. This paper presents an efficient hardware systolic accelerator for RBLWE-based PQC, targeting high-performance applications. We have briefly given the algorithmic background for the proposed design. Then, we have transferred the proposed algorithmic operation into a new systolic accelerator. Lastly, field-programmable gate array (FPGA) implementation results have confirmed the efficiency of the proposed accelerator.  more » « less
Award ID(s):
2020625
PAR ID:
10464948
Author(s) / Creator(s):
; ; ;
Date Published:
Journal Name:
2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Page Range / eLocation ID:
5 to 6
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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