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1. Magnetic domain wall neuron with intrinsic leaking and lateral inhibition capability

   https://doi.org/10.1117/12.2528218  

   Brigner, Wesley H.; Hassan, Naimul; Hu, Xuan; Jiang-Wei, Lucian; Akinola, Otitoaleke G.; Garcia-Sanchez, Felipe; Pasquale, Massimo; Bennett, Christopher H.; Incorvia, Jean Anne; Friedman, Joseph S. (September 2019, SPIE Spintronics XII)

   The challenge of developing an efficient artificial neuron is impeded by the use of external CMOS circuits to perform leaking and lateral inhibition. The proposed leaky integrate-and-fire neuron based on the three terminal magnetic tunnel junction (3T-MTJ) performs integration by pushing its domain wall (DW) with spin-transfer or spin-orbit torque. The leaking capability is achieved by pushing the neurons’ DWs in the direction opposite of integration using a stray field from a hard ferromagnet or a non-uniform energy landscape resulting from shape or anisotropy variation. Firing is performed by the MTJ stack. Finally, analog lateral inhibition is achieved by dipolar field repulsive coupling from each neuron. An integrating neuron thus pushes slower neighboring neurons’ DWs in the direction opposite of integration. Applying this lateral inhibition to a ten-neuron output layer within a neuromorphic crossbar structure enables the identification of handwritten digits with 94% accuracy. 

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2. NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs

   https://doi.org/10.1109/ISCA45697.2020.00039  

   Singh, Sonali; Sarma, Anup; Jao, Nicholas; Pattnaik, Ashutosh; Lu, Sen; Yang, Kezhou; Sengupta, Abhronil; Narayanan, Vijaykrishnan; Das, Chita R. (May 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA))

   null (Ed.)

   Brain-inspired cognitive computing has so far followed two major approaches - one uses multi-layered artificial neural networks (ANNs) to perform pattern-recognition-related tasks, whereas the other uses spiking neural networks (SNNs) to emulate biological neurons in an attempt to be as efficient and fault-tolerant as the brain. While there has been considerable progress in the former area due to a combination of effective training algorithms and acceleration platforms, the latter is still in its infancy due to the lack of both. SNNs have a distinct advantage over their ANN counterparts in that they are capable of operating in an event-driven manner, thus consuming very low power. Several recent efforts have proposed various SNN hardware design alternatives, however, these designs still incur considerable energy overheads.In this context, this paper proposes a comprehensive design spanning across the device, circuit, architecture and algorithm levels to build an ultra low-power architecture for SNN and ANN inference. For this, we use spintronics-based magnetic tunnel junction (MTJ) devices that have been shown to function as both neuro-synaptic crossbars as well as thresholding neurons and can operate at ultra low voltage and current levels. Using this MTJ-based neuron model and synaptic connections, we design a low power chip that has the flexibility to be deployed for inference of SNNs, ANNs as well as a combination of SNN-ANN hybrid networks - a distinct advantage compared to prior works. We demonstrate the competitive performance and energy efficiency of the SNNs as well as hybrid models on a suite of workloads. Our evaluations show that the proposed design, NEBULA, is up to 7.9× more energy efficient than a state-of-the-art design, ISAAC, in the ANN mode. In the SNN mode, our design is about 45× more energy-efficient than a contemporary SNN architecture, INXS. Power comparison between NEBULA ANN and SNN modes indicates that the latter is at least 6.25× more power-efficient for the observed benchmarks. 

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3. Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations

   Shihui Yin, Shreyas K. (October 2017, Biomedical Circuits and Systems Conference)

   We present a new back propagation based training algorithm for discrete-time spiking neural networks (SNN). Inspired by recent deep learning algorithms on binarized neural networks, binary activation with a straight-through gradient estimator is used to model the leaky integrate-fire spiking neuron, overcoming the difficulty in training SNNs using back propagation. Two SNN training algorithms are proposed: (1) SNN with discontinuous integration, which is suitable for rate-coded input spikes, and (2) SNN with continuous integration, which is more general and can handle input spikes with temporal information. Neuromorphic hardware designed in 28nm CMOS exploits the spike sparsity and demonstrates high classification accuracy (>98% on MNIST) and low energy (51.4–773 nJ/image). 

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4. Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel Junction Logic

   https://doi.org/10.1109/ISCAS45731.2020.9180675  

   Hu, Xuan; Edwards, Alexander J.; Xiao, T. Patrick; Bennett, Christopher H.; Incorvia, Jean Anne; Marinella, Matthew J.; Friedman, Joseph S. (October 2020, IEEE International Symposium on Circuits and Systems)

   null (Ed.)

   The domain wall-magnetic tunnel junction (DW-MTJ) is a spintronic device that enables efficient logic circuit design because of its low energy consumption, small size, and non-volatility. Furthermore, the DW-MTJ is one of the few spintronic devices for which a direct cascading mechanism is experimentally demonstrated without any extra buffers; this enables potential design and fabrication of a large-scale DW-MTJ logic system. However, DW-MTJ logic relies on the conversion between electrical signals and magnetic states which is sensitive to process imperfection. Therefore, it is important to analyze the robustness of such DW-MTJ devices to anticipate the system reliability before fabrication. Here we propose a new DW-MTJ model that integrates the impacts of process variation to enable the analysis and optimization of DW-MTJ logic. This will allow circuit and device design that enhances the robustness of DW-MTJ logic and advances the development of energy-efficient spintronic computing systems. 

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5. Lateral inhibition in magnetic domain wall racetrack arrays for neuromorphic computing

   https://doi.org/10.1117/12.2568870  

   Cui, Can; Akinola, Otitoaleke G.; Hassan, Naimul; Bennett, Christopher H.; Marinella, Matthew J.; Friedman, Joseph S.; Incorvia, Jean Anne (August 2020, Proc. SPIE, Spintronics XIII)

   Drouhin, Henri-Jean M.; Wegrowe, Jean-Eric; Razeghi, Manijeh (Ed.)

   Neuromorphic computing captures the quintessential neural behaviors of the brain and is a promising candidate for the beyond-von Neumann computer architectures, featuring low power consumption and high parallelism. The neuronal lateral inhibition feature, closely associated with the biological receptive eld, is crucial to neuronal competition in the nervous system as well as its neuromorphic hardware counterpart. The domain wall - magnetic tunnel junction (DW-MTJ) neuron is an emerging spintronic arti cial neuron device exhibiting intrinsic lateral inhibition. This work discusses lateral inhibition mechanism of the DW-MTJ neuron and shows by micromagnetic simulation that lateral inhibition is eciently enhanced by the Dzyaloshinskii-Moriya interaction (DMI). 

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