Abstract New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm2V−1s−1, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm2V–1s–1and a subthreshold slope of 0.29 V dec–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐kgate insulator (ALD Al2O3), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates. 
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                            Threshold voltage control with high-temperature gate-oxide annealing in ultrawide bandgap AlGaN-channel MOSHFETs
                        
                    
    
            Abstract We report threshold voltage (VTH) control in ultrawide bandgap Al0.4Ga0.6N-channel metal oxide semiconductor heterostructure field-effect transistors using a high-temperature (300 °C) anneal of the high-kZrO2gate-insulator. Annealing switched the polarity of the fixed charges at the ZrO2/AlGaN interface from +5.5 × 1013cm−2to −4.2 × 1013cm−2, pinningVTHat ∼ (−12 V), reducing gate leakage by ∼103, and improving subthreshold swing 2× (116 mV decade−1). It also enabled the gate to repeatedly withstand voltages from −40 to +18 V, allowing the channel to be overdriven doubling the peak currents to ∼0.5 A mm−1. 
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                            - Award ID(s):
- 1831954
- PAR ID:
- 10483529
- Publisher / Repository:
- The Japan Society of Applied Physics
- Date Published:
- Journal Name:
- Applied Physics Express
- Volume:
- 15
- Issue:
- 10
- ISSN:
- 1882-0778
- Page Range / eLocation ID:
- 104001
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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