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1. Exploiting DRAM Latency Variations for Generating True Random Numbers

   https://doi.org/10.1109/ICCE.2019.8662060  

   Bahar Talukder, B M; Kerns, Joseph; Ray, Biswajit; Morris, Thomas; Rahman, Md Tauhidur (March 2019, Exploiting DRAM Latency Variations for Generating True Random Numbers)

   True random number generator (TRNG) plays a vital role in a variety of security applications and protocols. The security and privacy of an asset rely on encryption, which solely depends on the quality of random numbers. Memory chips are widely used for generating random numbers because of their prevalence in modern electronic systems. Unfortunately, existing Dynamic Random-access Memory (DRAM)-based TRNGs produce random numbers with either limited entropy or poor throughput. In this paper, we propose a DRAM-latency based TRNG that generates high-quality random numbers. The silicon results from Samsung and Micron DDR3 DRAM modules show that our proposed DRAM-latency based TRNG is robust (against different operating conditions and environmental variations) and acceptably fast. 

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2. An Integrated TRNG-PUF Architecture based on Photovoltaic Solar Cells

   https://doi.org/10.1109/MCE.2020.3019762  

   Degada, Amit; Thapliyal, Himanshu (August 2020, IEEE Consumer Electronics Magazine)

   null (Ed.)

   The objective of the article is to present an integrated True Random Number Generator (TRNG) and Physically Unclonable Function (PUF) architecture using Photovoltaic solar cells. We illustrate that the Photovoltaic (PV) solar cell sensor response can be engineered into dynamic (TRNG) and static responses (PUF). The proposed prototype uses the iterative Von Neumann post-processing scheme to produce random bits with 34% better throughput compared to a single Von Neumann operation. The random bit quality was checked by statistical test suites from the National Institute of Science and Technology (NIST) and achieves an average p-value of 0.45 at all variations in light intensity. The PUF response achieves 92.13% reliability and 50.91% uniformity. The integrated TRNG-PUF architecture is beneficial for resource-constrained Cyber-Physical System (CPS). 

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3. Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud

   Li, Xiang; Stanwicks, Peter; Provelengios, George; Tessier, Russell; Holcomb, Daniel (December 2020, International Conference on Field Programmable Technology)

   null (Ed.)

   In this paper we present and evaluate a true random number generator (TRNG) design that is compatible with the restrictions imposed by cloud-based FPGA providers such as Amazon Web Services (AWS) EC2 F1. Because cloud FPGA providers disallow the ring oscillator circuits that conventionally generate TRNG entropy, our design is oscillator-free and uses clock jitter as its entropy source. The clock jitter is harvested with a time-to-digital converter (TDC) and a controllable delay line that is continuously tuned to compensate for process, voltage, and temperature variations. After describing the design, we present and validate a stochastic model that conservatively quantifies its worst-case entropy. We deploy and model the design in the cloud on 60 EC2 F1 FPGA instances to ensure sufficient randomness is captured. TRNG entropy is further validated using NIST test suites, and experiments are performed to understand how the TRNG responds to on-die power attacks that disturb the FPGA supply voltage in the vicinity of the TRNG. 

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4. Harnessing Uncertainty in Photoresistor Sensor for True Random Number Generation in IoT Devices

   https://doi.org/10.1109/ICCE46568.2020.9042967  

   Degada, Amit; Thapliyal, Himanshu (January 2020, 2020 IEEE International Conference on Consumer Electronics (ICCE))

   null (Ed.)

   Internet of Things (IoT) has facilitated the connection of many smart devices via internet. Recent cyberattacks have shown that resource constrained IoT nodes are easy prey that lead towards compromising the secrecy of the data and vulnerabilities could be exploited remotely to take control of safety-critical systems. Photoresistor sensors have applications in IoT systems, such as smart street lighting, intelligent cameras, light activated smart consumer electronics, smart home, smart healthcare, etc. Building hardware security primitives, such as True Random Number Generator (TRNG), based on the intrinsic properties of photoresistor would be a novel direction to develop cost-savvy IoT security primitives. Therefore, this paper proposes a TRNG prototype that is devised from uncertainty presents in photoresistor sensors. The proposed TRNG prototype does not require any complex interfacing for preprocessing the weak signal, thereby reducing the unnecessary delay and the recurring hardware cost. The proposed prototype employs the novel approach of additive scrambling that aids to sample sensors at a higher rate. The proposed TRNG has an average random bit generation rate of 8 kbps that is better than the recent work in the literature. The quality of randomness was validated by 15 test batteries of NIST STS test. 

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5. Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud

   https://doi.org/10.1145/3487554  

   Li, Xiang; Stanwicks, Peter; Provelengios, George; Tessier, Russell; Holcomb, Daniel (March 2023, ACM Transactions on Reconfigurable Technology and Systems)

   In this article, we present and evaluate a true random number generator (TRNG) design that is compatible with the restrictions imposed by cloud-based Field Programmable Gate Array (FPGA) providers such as Amazon Web Services (AWS) EC2 F1. Because cloud FPGA providers disallow the ring oscillator circuits that conventionally generate TRNG entropy, our design is oscillator-free and uses clock jitter as its entropy source. The clock jitter is harvested with a time-to-digital converter (TDC) and a controllable delay line that is continuously tuned to compensate for process, voltage, and temperature variations. After describing the design, we present and validate a stochastic model that conservatively quantifies its worst-case entropy. We deploy and model the design in the cloud on 60 EC2 F1 FPGA instances to ensure sufficient randomness is captured. TRNG entropy is further validated using NIST test suites, and experiments are performed to understand how the TRNG responds to on-die power attacks that disturb the FPGA supply voltage in the vicinity of the TRNG. After introducing and validating our basic TRNG design, we introduce and validate a new variant that uses four instances of a linkable sampling module to increase the entropy per sample and improve throughput. The new variant improves throughput by 250% at a modest 17% increase in CLB count. 

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