More Like this

1. Benchmarking RRAM Crossbar Arrays for Epileptic Seizure Prediction

   https://doi.org/10.1109/MWSCAS60917.2024.10658668  

   Khan, Ahmedul; Varnosfaderani, Shiva Maleki; Alhawari, Mohammad; Tutuncuoglu, Gozde (August 2024, IEEE)

   This paper explores an energy-efficient resistive random access memory (RRAM) crossbar array framework for predicting epileptic seizures using the CHB-MIT electroencephalogram (EEG) dataset. RRAMs have significant potential for in-memory computing, offering a promising solution to overcome the limitations of the traditional Von Neumann architecture. By integrating a domain-specific feature extraction approach and evaluating the optimal RRAM hardware parameters using the NeuroSim+ benchmarking platform, we assess the performance of RRAM crossbars for predicting epileptic seizures. Our proposed workflow achieves accuracy levels above 80% despite the EEG data being quantized to 1-bit, highlighting the robustness and efficiency of our approach for epileptic seizure prediction 

   more » « less
2. RipTide: A Programmable, Energy-Minimal Dataflow Compiler and Architecture

   https://doi.org/10.1109/MICRO56248.2022.00046  

   Gobieski, Graham; Ghosh, Souradip; Heule, Marijn; Mowry, Todd; Nowatzki, Tony; Beckmann, Nathan; Lucia, Brandon (October 2022, 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO))

   Emerging sensing applications create an unprecedented need for energy efficiency in programmable processors. To achieve useful multi-year deployments on a small battery or energy harvester, these applications must avoid off-device communication and instead process most data locally. Recent work has proven coarse-grained reconfigurable arrays (CGRAs) as a promising architecture for this domain. Unfortunately, nearly all prior CGRAs support only computations with simple control flow and no memory aliasing (e.g., affine inner loops), causing an Amdahl efficiency bottleneck as non-trivial fractions of programs must run on an inefficient von Neumann core.RipTide is a co-designed compiler and CGRA architecture that achieves both high programmability and extreme energy efficiency, eliminating this bottleneck. RipTide provides a rich set of control-flow operators that support arbitrary control flow and memory access on the CGRA fabric. RipTide implements these primitives without tagged tokens to save energy; this requires careful ordering analysis in the compiler to guarantee correctness. RipTide further saves energy and area by offloading most control operations into its programmable on-chip network, where they can re-use existing network switches. RipTide’s compiler is implemented in LLVM, and its hardware is synthesized in Intel 22FFL. RipTide compiles applications written in C while saving 25% energy v. the state-of-the-art energy-minimal CGRA and 6.6 × energy v. a von Neumann core. 

   more » « less
3. Cloud FPGA Security with RO-Based Primitives

   Tian, Shanquan; Krzywosz, Andrew; Giechaskiel, Ilias; Szefer, Jakub (December 2020, International Conference on Field-Programmable Technology (FPT))

   null (Ed.)

   Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are common primitives that can increase the security of user logic on FPGAs. They are typically constructed using Ring Oscillators (ROs). However, PUF and TRNG primitives are not currently available on Cloud FPGAs as some commercial Cloud FPGA providers prohibit deploying ROs implemented using Lookup Tables (LUTs). To aid in bringing RO-based PUFs and TRNGs to commercial Cloud FPGAs, this work implements and evaluates PUFs and TRNGs built using ROs that incorporate latches and flip-flops. The primitives are tested on Amazon's commercial F1 Cloud FPGAs. The designs are the first constructive uses of ROs in Cloud FPGAs and are available under an open-source license. 

   more » « less
4. A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers

   https://doi.org/10.1145/3649476.3658732  

   Singh, Gian; Vrudhula, Sarma (June 2024, ACM)

   Transformers-based language models have achieved remarkable accuracy in various NLP tasks, employing self-attention mecha- nisms primarily based on matrix multiplication. However, their significant size leads to data movement issues, causing latency and energy efficiency challenges in conventional Von-Neumann systems. To mitigate these issues, several in-memory and near- memory architectures have been proposed. This paper introduces PACT-3D, a near-memory architecture featuring novel computing units integrated with DRAM banks. PACT-3D significantly reduces latency by 1.7× and improves energy efficiency by 18.7× compared to state-of-the-art near-memory architectures. 

   more » « less
5. >10% solar-to-hydrogen efficiency unassisted water splitting on ALD-protected silicon heterojunction solar cells

   https://doi.org/10.1039/c9se00110g  

   Tan, Chor Seng; Kemp, Kyle W.; Braun, Michael R.; Meng, Andrew C.; Tan, Wanliang; Chidsey, Chris E.; Ma, Wen; Moghadam, Farhad; McIntyre, Paul C. (May 2019, Sustainable Energy & Fuels)

   Solar water splitting using photoelectrochemical cells (PEC's) is a promising pathway toward clean and sustainable storage of renewable energy. Practical realization of solar-driven synthesis of hydrogen and oxygen integrating light absorption and electrolysis of water has been challenging because of (1) the limited stability of good photovoltaic materials under the required electrochemical conditions, and (2) photovoltaic efficiency losses due to light absorption by catalysts, the electrolyte, and generated bubbles, or reflection at their various interfaces. Herein, we evaluate a novel integrated solar water splitting architecture using efficient silicon heterojunction photovoltaic cells that avoids such losses and exhibits a solar-to-hydrogen (STH) efficiency in excess of 10%. Series-connected silicon Heterojunction with Intrinsic Thin layer (HIT) cells generate sufficient photovoltage for unassisted water splitting, with one of the cells acting as the photocathode. Platinum is deposited on the back (dark) junction of this HIT cell as the catalyst for the hydrogen evolution reaction (HER). The photocathode is protected from corrosion by a TiO 2 layer deposited by atomic layer deposition (ALD) interposed between the HIT cell and the Pt, enabling stable operation for >120 hours. Combined with oxygen evolution reaction (OER) catalysts deposited on a porous metal dark anode, these PEC's achieve stable water splitting with a record high STH efficiency for an integrated silicon photosynthesis device. 

   more » « less