Continuous device downsizing and circuit complexity have motivated atomic-scale tuning of memristors. Herein, we report atomically tunable Pd/M1/M2/Al ultrathin (<2.5 nm M1/M2 bilayer oxide thickness) memristors using in vacuo atomic layer deposition by controlled insertion of MgO atomic layers into pristine Al2O3atomic layer stacks guided by theory predicted Fermi energy lowering leading to a higher high state resistance (HRS) and a reduction of oxygen vacancy formation energy. Excitingly, memristors with HRS and on/off ratio increasing exponentially with M1/M2 thickness in the range 1.2–2.4 nm have been obtained, illustrating tunneling mechanism and tunable on/off ratio in the range of 10–104. Further dynamic tunability of on/off ratio by electric field is possible by designing of the atomic M2 layer and M1/M2 interface. This result probes ways in the design of memristors with atomically tunable performance parameters.
Ultrathin (sub-2 nm) Al2O3/MgO memristors were recently developed using an
- NSF-PAR ID:
- 10498322
- Publisher / Repository:
- IOP Publishing
- Date Published:
- Journal Name:
- Nano Express
- Volume:
- 5
- Issue:
- 2
- ISSN:
- 2632-959X
- Format(s):
- Medium: X Size: Article No. 025001
- Size(s):
- ["Article No. 025001"]
- Sponsoring Org:
- National Science Foundation
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By mimicking biomimetic synaptic processes, the success of artificial intelligence (AI) has been astounding with various applications such as driving automation, big data analysis, and natural-language processing.[1-4] Due to a large quantity of data transmission between the separated memory unit and the logic unit, the classical computing system with von Neumann architecture consumes excessive energy and has a significant processing delay.[5] Furthermore, the speed difference between the two units also causes extra delay, which is referred to as the memory wall.[6, 7] To keep pace with the rapid growth of AI applications, enhanced hardware systems that particularly feature an energy-efficient and high-speed hardware system need to be secured. The novel neuromorphic computing system, an in-memory architecture with low power consumption, has been suggested as an alternative to the conventional system. Memristors with analog-type resistive switching behavior are a promising candidate for implementing the neuromorphic computing system since the devices can modulate the conductance with cycles that act as synaptic weights to process input signals and store information.[8, 9]
The memristor has sparked tremendous interest due to its simple two-terminal structure, including top electrode (TE), bottom electrode (BE), and an intermediate resistive switching (RS) layer. Many oxide materials, including HfO2, Ta2O5, and IGZO, have extensively been studied as an RS layer of memristors. Silicon dioxide (SiO2) features 3D structural conformity with the conventional CMOS technology and high wafer-scale homogeneity, which has benefited modern microelectronic devices as dielectric and/or passivation layers. Therefore, the use of SiO2as a memristor RS layer for neuromorphic computing is expected to be compatible with current Si technology with minimal processing and material-related complexities.
In this work, we proposed SiO2-based memristor and investigated switching behaviors metallized with different reduction potentials by applying pure Cu and Ag, and their alloys with varied ratios. Heavily doped p-type silicon was chosen as BE in order to exclude any effects of the BE ions on the memristor performance. We previously reported that the selection of TE is crucial for achieving a high memory window and stable switching performance. According to the study which compares the roles of Cu (switching stabilizer) and Ag (large switching window performer) TEs for oxide memristors, we have selected the TE materials and their alloys to engineer the SiO2-based memristor characteristics. The Ag TE leads to a larger memory window of the SiO2memristor, but the device shows relatively large variation and less reliability. On the other hand, the Cu TE device presents uniform gradual switching behavior which is in line with our previous report that Cu can be served as a stabilizer, but with small on/off ratio.[9] These distinct performances with Cu and Ag metallization leads us to utilize a Cu/Ag alloy as the TE. Various compositions of Cu/Ag were examined for the optimization of the memristor TEs. With a Cu/Ag alloying TE with optimized ratio, our SiO2based memristor demonstrates uniform switching behavior and memory window for analog switching applications. Also, it shows ideal potentiation and depression synaptic behavior under the positive/negative spikes (pulse train).
In conclusion, the SiO2memristors with different metallization were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of memristor, we integrated Cu, Ag and Cu/Ag alloy as TEs and compared the switch characteristics. Our encouraging results clearly demonstrate that SiO2with Cu/Ag is a promising memristor device with synaptic switching behavior in neuromorphic computing applications.
Acknowledgement This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 22011044) by KRISS.
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et al. , Physica Status Solidi (RRL) - Rapid Research Letters, pssr.202200075R1, In press, 2022. -
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Nanoscale spinel lithium manganese oxide is of interest as a high‐rate cathode material for advanced battery technologies among other electrochemical applications. In this work, the synthesis of ultrathin films of spinel lithium manganese oxide (LiMn2O4) between 20 and 200 nm in thickness by room‐temperature electrochemical conversion of MnO grown by atomic layer deposition (ALD) is demonstrated. The charge storage properties of LiMn2O4thin films in electrolytes containing Li+, Na+, K+, and Mg2+are investigated. A unified electrochemical band‐diagram (UEB) analysis of LiMn2O4informed by screened hybrid density functional theory calculations is also employed to expand on existing understanding of the underpinnings of charge storage and stability in LiMn2O4. It is shown that the incorporation of Li+or other cations into the host manganese dioxide spinel structure (λ‐MnO2) stabilizes electronic states from the conduction band which align with the known redox potentials of LiMn2O4. Furthermore, the cyclic voltammetry experiments demonstrate that up to 30% of the capacity of LiMn2O4arises from bulk electronic charge‐switching which does not require compensating cation mass transport. The hybrid ALD‐electrochemical synthesis, UEB analysis, and unique charge storage mechanism described here provide a fundamental framework to guide the development of future nanoscale electrode materials for ion‐incorporation charge storage.
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Abstract New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm2V−1s−1, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm2V–1s–1and a subthreshold slope of 0.29 V dec–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐
k gate insulator (ALD Al2O3), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates. -
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Wafer-scale synthesis of p-type TMD films is critical for its commercialization in next-generation electro/optoelectronics. In this work, wafer-scale intrinsic n-type WS2films and in situ Nb-doped p-type WS2films were synthesized through atomic layer deposition (ALD) on 8-inch
α -Al2O3/Si wafers, 2-inch sapphire, and 1 cm2GaN substrate pieces. The Nb doping concentration was precisely controlled by altering cycle number of Nb precursor and activated by postannealing. WS2n-FETs and Nb-doped p-FETs with different Nb concentrations have been fabricated using CMOS-compatible processes. X-ray photoelectron spectroscopy, Raman spectroscopy, and Hall measurements confirmed the effective substitutional doping with Nb. The on/off ratio and electron mobility of WS2n-FET are as high as 105and 6.85 cm2 V-1 s-1, respectively. In WS2p-FET with 15-cycle Nb doping, the on/off ratio and hole mobility are 10 and 0.016 cm2 V-1 s-1, respectively. The p-n structure based on n- and p- type WS2films was proved with a 104rectifying ratio. The realization of controllablein situ Nb-doped WS2films paved a way for fabricating wafer-scale complementary WS2FETs.
