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Abstract The transition towards designs which co-package electronic and photonic die together in data center switch packages has created a scaling path to Petabyte per second (Pbps) input/output (I/O) in such systems. In a co-packaged design, the scaling of bandwidth, cost, and energy will be governed by the number of optical I/O channels and the data rate per channel. While optical communication provide an opportunity to exploit wavelength division multiplexing (WDM) to scale data rate, the limited 127 µm pitch of V-groove based single mode fiber arrays and the use of active alignment and bonding for their packaging present challenges to scaling the number of optical channels. Flip-chip optical couplers which allow for low loss, broadband operation and automated passive assembly represent a solution for continued scaling. In this paper, we propose a novel scheme to vertically couple between silicon based waveguides on separate chips using graded index (GRIN) couplers in combination with an evanescent coupler. Simulation results using a 3D Finite-Difference Time-Domain (FDTD) solver are presented, demonstrating coupling losses as low as 0.35 dB for a chip-to-chip gap of 11 µm; 1-dB vertical and lateral alignment tolerances of approximately 2.45 µm and ± 2.66 µm, respectively; and a possible 1-dB bandwidth of greater than 1500 nm. These results demonstrate the potential of our coupler as a universal interface in future co-packaged optics systems.
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High density vertical optical interconnects for passive assembly
The co-packaging of optics and electronics provides a potential path forward to achieving beyond 50 Tbps top of rack switch packages. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical transceivers (TxRx) per package as opposed to transistor shrink. Due to the large footprint of optical components relative to their electronic counterparts, the vertical stacking of optical TxRx chips in a co-packaged optics design will become a necessity. As a result, development of efficient, dense, and wide alignment tolerance chip-to-chip optical couplers will be an enabling technology for continued TxRx scaling. In this paper, we propose a novel scheme to vertically couple into standard 220 nm silicon on insulator waveguides from 220 nm silicon nitride on glass waveguides using overlapping, inverse double tapers. Simulation results using Lumerical’s 3D Finite Difference Time Domain solver are presented, demonstrating insertion losses below -0.13 dB for an inter-chip spacing of 1µm; 1 dB vertical and lateral alignment tolerances of approximately 2.6µm and ± 2.8µm, respectively; a greater than 300 nm 1 dB bandwidth; and 1 dB twist and tilt tolerances of approximately ± 2.3 degrees and 0.4 degrees, respectively. These results demonstrate the potential of our coupler for use in co-packaged designs requiring high performance, high density, CMOS compatible out of plane optical connections.
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- Award ID(s):
- 2236093
- PAR ID:
- 10497829
- Publisher / Repository:
- Optics Express Journal
- Date Published:
- Journal Name:
- Optics Express
- Edition / Version:
- 1.0
- Volume:
- 31
- Issue:
- 2
- ISSN:
- 1094-4087
- Page Range / eLocation ID:
- 2816
- Subject(s) / Keyword(s):
- Co-packaged Optics CMOS-compatible Simulation Out of plane optical connection
- Format(s):
- Medium: X Size: 4.8MB Other: pdf
- Size(s):
- 4.8MB
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1364/OE.475726
