Full-duplex (FD) wireless is an emerging wireless communication paradigm where the transmitter and the receiver operate simultaneously at the same frequency. One major challenge in realizing FD wireless is the interference of the TX signal saturating the receiver, commonly referred to self-interference (SI). Traditionally, self-interference cancellation (SIC) is achieved in the antenna, RF/analog, and digital domains. In the antenna domain, SIC can be achieved using a pair of separate TX and RX antennas, or using a single antenna shared by the TX and RX through a magnetic circulator, which is usually bulky, expensive, and not integrable with CMOS. Recent advances, however, have shown the feasibility of realizing high-performance non-reciprocal circulators in CMOS based on spatio-temporal modulation. In this work, we demonstrate a high power handling FD radio using a USRP SDR which employs SIC (i) at the antenna interface using a watt-level power-handling CMOS integrated, magnetic-free circulator, (ii) in the RF domain using a compact RF canceler, and (iii) in the digital domain. Our prototyped FD radio achieves +95 dB overall SIC at +15dBm TX power level. We analyze the effects of the circulator TX-RX non-linearity on the total achievable SIC
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Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines
The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas active implementations suffer from noise and linearity penalties. In this work, we leverage time-interleaved multi-path switched-capacitor (SC) circuits to provide large wideband delays with a small form factor and low power (LP) consumption to implement RF and baseband (BB) cancelers in an FD receiver (RX). We utilize capacitor stacking to obtain passive voltage gain to compensate for the loss of these delay elements, thus permitting an increased number of interleaved paths and, hence, a higher delay. Furthermore, to reduce the RX noise figure (NF) penalty due to injecting the cancellation signal into the receiver, we introduce a novel low-noise trans-impedance amplifier (LNTA) architecture, which injects the cancellation signal into RX and also accomplishes finite impulse response (FIR) filter weighting and summation. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 0.1 to 1 GHz. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging
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- PAR ID:
- 10508946
- Publisher / Repository:
- IEEE
- Date Published:
- Journal Name:
- IEEE Journal of Solid-State Circuits
- ISSN:
- 0018-9200
- Page Range / eLocation ID:
- 1 to 16
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Full-duplex (FD) wireless is an emerging wireless communication paradigm where the transmitter and the receiver operate simultaneously at the same frequency. One major challenge in realizing FD wireless is the interference of the TX signal saturating the receiver, commonly referred to self-interference (SI). Traditionally, self-interference cancellation (SIC) is achieved in the antenna, RF/analog, and digital domains. In the antenna domain, SIC can be achieved using a pair of separate TX and RX antennas, or using a single antenna shared by the TX and RX through a magnetic circulator, which is usually bulky, expensive, and not integrable with CMOS. Recent advances, however, have shown the feasibility of realizing high-performance non-reciprocal circulators in CMOS based on spatio-temporal modulation. In this work, we demonstrate a high power handling FD radio using a USRP SDR which employs SIC (i) at the antenna interface using a watt-level power-handling CMOS integrated, magnetic-free circulator, (ii) in the RF domain using a compact RF canceler, and (iii) in the digital domain. Our prototyped FD radio achieves +95 dB overall SIC at +15dBm TX power level. We analyze the effects of the circulator TX-RX non-linearity on the total achievable SIC.more » « less
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