Full-duplex (FD) wireless is an emerging wireless communication paradigm where the transmitter and the receiver operate simultaneously at the same frequency. One major challenge in realizing FD wireless is the interference of the TX signal saturating the receiver, commonly referred to self-interference (SI). Traditionally, self-interference cancellation (SIC) is achieved in the antenna, RF/analog, and digital domains. In the antenna domain, SIC can be achieved using a pair of separate TX and RX antennas, or using a single antenna shared by the TX and RX through a magnetic circulator, which is usually bulky, expensive, and not integrable with CMOS. Recent advances, however, have shown the feasibility of realizing high-performance non-reciprocal circulators in CMOS based on spatio-temporal modulation. In this work, we demonstrate a high power handling FD radio using a USRP SDR which employs SIC (i) at the antenna interface using a watt-level power-handling CMOS integrated, magnetic-free circulator, (ii) in the RF domain using a compact RF canceler, and (iii) in the digital domain. Our prototyped FD radio achieves +95 dB overall SIC at +15dBm TX power level. We analyze the effects of the circulator TX-RX non-linearity on the total achievable SIC
more »
« less
This content will become publicly available on January 1, 2025
Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines
The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas active implementations suffer from noise and linearity penalties. In this work, we leverage time-interleaved multi-path switched-capacitor (SC) circuits to provide large wideband delays with a small form factor and low power (LP) consumption to implement RF and baseband (BB) cancelers in an FD receiver (RX). We utilize capacitor stacking to obtain passive voltage gain to compensate for the loss of these delay elements, thus permitting an increased number of interleaved paths and, hence, a higher delay. Furthermore, to reduce the RX noise figure (NF) penalty due to injecting the cancellation signal into the receiver, we introduce a novel low-noise trans-impedance amplifier (LNTA) architecture, which injects the cancellation signal into RX and also accomplishes finite impulse response (FIR) filter weighting and summation. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 0.1 to 1 GHz. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging
more »
« less
- Award ID(s):
- 2148128
- NSF-PAR ID:
- 10508946
- Publisher / Repository:
- IEEE
- Date Published:
- Journal Name:
- IEEE Journal of Solid-State Circuits
- ISSN:
- 0018-9200
- Page Range / eLocation ID:
- 1 to 16
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
Full-duplex (FD) wireless is an emerging wireless communication paradigm where the transmitter and the receiver operate simultaneously at the same frequency. One major challenge in realizing FD wireless is the interference of the TX signal saturating the receiver, commonly referred to self-interference (SI). Traditionally, self-interference cancellation (SIC) is achieved in the antenna, RF/analog, and digital domains. In the antenna domain, SIC can be achieved using a pair of separate TX and RX antennas, or using a single antenna shared by the TX and RX through a magnetic circulator, which is usually bulky, expensive, and not integrable with CMOS. Recent advances, however, have shown the feasibility of realizing high-performance non-reciprocal circulators in CMOS based on spatio-temporal modulation. In this work, we demonstrate a high power handling FD radio using a USRP SDR which employs SIC (i) at the antenna interface using a watt-level power-handling CMOS integrated, magnetic-free circulator, (ii) in the RF domain using a compact RF canceler, and (iii) in the digital domain. Our prototyped FD radio achieves +95 dB overall SIC at +15dBm TX power level. We analyze the effects of the circulator TX-RX non-linearity on the total achievable SIC.more » « less
-
Full-duplex (FD) wireless and phased arrays are both promising techniques that can significantly improve data rates in future wireless networks. However, integrating FD with transmit (Tx) and receive (Rx) phased arrays is extremely challenging, due to the large number of self-interference (SI) channels. Previous work relies on either RF canceller hardware or on analog/digital Tx beamforming (TxBF) to achieve SI cancellation (SIC). However, Rx beamforming (RxBF) and the data rate gain introduced by FD nodes employing beamforming have not been considered yet. We study FD phased arrays with joint TxBF and RxBF with the objective of achieving improved FD data rates. The key idea is to carefully select the TxBF and RxBF weights to achieve wideband RF SIC in the spatial domain with minimal TxBF and RxBF gain losses. Essentially, TxBF and RxBF are repurposed, thereby not requiring specialized RF canceller circuitry. We formulate the corresponding optimization problem and develop an iterative algorithm to obtain an approximate solution with provable performance guarantees. Using SI channel measurements and datasets, we extensively evaluate the performance of the proposed approach in different use cases under various network settings. The results show that an FD phased array with 9/36/72 elements can cancel the total SI power to below the noise floor with sum TxBF and RxBF gain losses of 10.6/7.2/6.9 dB, even at Tx power level of 30 dBm. Moreover, the corresponding FD rate gains are at least 1.33/1.66/1.68×more » « less
-
Full-duplex (FD) wireless and phased arrays are both promising techniques that can significantly improve data rates in future wireless networks. However, integrating FD with transmit (Tx) and receive (Rx) phased arrays is extremely challenging, due to the large number of self-interference (SI) channels. Previous work relies on either RF canceller hardware or on analog/digital Tx beamforming (TxBF) to achieve SI cancellation (SIC). However, Rx beamforming (RxBF) and the data rate gain introduced by FD nodes employing beamforming have not been considered yet. We study FD phased arrays with joint TxBF and RxBF with the objective of achieving improved FD data rates. The key idea is to carefully select the TxBF and RxBF weights to achieve wideband RF SIC in the spatial domain with minimal TxBF and RxBF gain losses. Essentially, TxBF and RxBF are repurposed, thereby not requiring specialized RF canceller circuitry. We formulate the corresponding optimization problem and develop an iterative algorithm to obtain an approximate solution with provable performance guarantees. Using SI channel measurements and datasets, we extensively evaluate the performance of the proposed approach in different use cases under various network settings. The results show that an FD phased array with 9/36/72 elements can cancel the total SI power to below the noise floor with sum TxBF and RxBF gain losses of 10.6/7.2/6.9 dB, even at Tx power level of 30 dBm. Moreover, the corresponding FD rate gains are at least 1.33/1.66/1.68×.more » « less
-
Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires tremendous amount of selfinterference (SI) cancellation. Recent advances in the RFIC community enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization (FDE), where RF filters channelize the SI signal path. Unlike other FD implementations, that mostly rely on delay lines, FDE-based cancellers can be realized in small-formfactor devices. However, the fundamental limits and higher layer challenges associated with these cancellers were not explored yet. Therefore, and in order to support the integration with a software-defined radio (SDR) and to facilitate experimentation in a testbed with several nodes, we design and implement an FDE-based RF canceller on a printed circuit board (PCB). We derive and experimentally validate the PCB canceller model and present a canceller configuration scheme based on an optimization problem. We then extensively evaluate the performance of the FDE-based FD radio in the SDR testbed. Experiments show that it achieves 95 dB overall SIC (52 dB from RF SIC) across 20 MHz bandwidth, and an average link-level FD gain of 1.87×. We also conduct experiments in: (i) uplink-downlink networks with inter-user interference, and (ii) heterogeneous networks with half-duplex and FD users. The experimental FD gains in the two types of networks confirm previous analytical results. They depend on the users’ SNR values and the number of FD users, and are 1.14×–1.25× and 1.25×–1.73×, respectively. Finally, we numerically evaluate and compare the RFIC and PCB implementations and study various design tradeoffs.more » « less
