PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration
- Award ID(s):
- 2336012
- PAR ID:
- 10511023
- Publisher / Repository:
- IEEE
- Date Published:
- Journal Name:
- Design, Automation & Test in Europe Conference & Exhibition (DATE)
- Page Range / eLocation ID:
- 1 to 6
- Format(s):
- Medium: X
- Location:
- Antwerp, Belgium
- Sponsoring Org:
- National Science Foundation
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Abstract We present a novel deep neural network (DNN) training scheme and resistive RAM (RRAM) in-memory computing (IMC) hardware evaluation towards achieving high accuracy against RRAM device/array variations and enhanced robustness against adversarial input attacks. We present improved IMC inference accuracy results evaluated on state-of-the-art DNNs including ResNet-18, AlexNet, and VGG with binary, 2-bit, and 4-bit activation/weight precision for the CIFAR-10 dataset. These DNNs are evaluated with measured noise data obtained from three different RRAM-based IMC prototype chips. Across these various DNNs and IMC chip measurements, we show that our proposed hardware noise-aware DNN training consistently improves DNN inference accuracy for actual IMC hardware, up to 8% accuracy improvement for the CIFAR-10 dataset. We also analyze the impact of our proposed noise injection scheme on the adversarial robustness of ResNet-18 DNNs with 1-bit, 2-bit, and 4-bit activation/weight precision. Our results show up to 6% improvement in the robustness to black-box adversarial input attacks.more » « less
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