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Title: INTIACC: A Programmable Floating-Point Accelerator for Partial Differential Equations
This article presents a 32-bit floating-point (FP32) programmable accelerator for solving a wide range of partial differential equations (PDEs) based on numerical integration methods. Compared to prior works that have fixed-point systems and are only applicable to specific types of PDEs, our proposed, integration accelerator for PDEs, named INTIACC, accelerator consists of 16 locally interconnected processing elements (PEs) where each PE is a fully programmable reduced instruction set computer (RISC) processor with an FP32 arithmetic logic unit (FP32 ALU) and a custom-designed instruction set architecture (ISA). These features enable INTIACC to generate solutions with high precision and a wide dynamic range and also allow users to implement different numerical algorithms to perform high-order integration methods and to evaluate nonlinear functions. In addition, we create a novel slow-global-fast-local clocking scheme in which PEs operate asynchronously with each other most of the time. We prototype the INTIACC test chip in 65 nm, with a core area of 0.975 mm2. Running at an average local clock frequency of 570 MHz at 1 V, it offers a single-precision computation throughput of 9.12 GFLOPS. Testing results show that with a similar energy-delay product, INTIACC is up to 40× faster than the prior state-of-the-art PDE solver.  more » « less
Award ID(s):
1840763
PAR ID:
10521633
Author(s) / Creator(s):
; ;
Editor(s):
Mathew, Sanu
Publisher / Repository:
IEEE
Date Published:
Journal Name:
IEEE Journal of Solid-State Circuits
ISSN:
0018-9200
Page Range / eLocation ID:
1 to 12
Subject(s) / Keyword(s):
32-bit floating point, boundary conditions (BCs), custom instruction set architecture (ISA), hybrid global-local clocking scheme, numerical integration, partial differential equations (PDEs), programmable accelerator
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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