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1. Architectural Modeling and Benchmarking for Digital DRAM PIM

   https://doi.org/10.1109/IISWC63097.2024.00030  

   Siddique, Farzana Ahmed; Guo, Deyuan; Fan, Zhenxing; Gholamrezaei, Mohammadhosein; Baradaran, Morteza; Ahmed, Alif; Abbot, Hugo; Durrer, Kyle; Nandagopal, Kumaresh; Ermovick, Ethan; et al (September 2024, IEEE)
2. Exploring PIM Architecture for High-performance Graph Pattern Mining

   https://doi.org/10.1109/LCA.2021.3103665  

   Su, Jiya; He, Linfeng; Jiang, Peng; Wang, Rujia (August 2021, IEEE Computer Architecture Letters)

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3. Accelerating Graph Computations on 3D NoC-enabled PIM Architectures

   https://doi.org/10.1145/3564290  

   Choudhury, Dwaipayan; Xiang, Lizhi; Rajam, Aravind Sukumaran; Kalyanaraman, Ananth; Pande, Partha Pratim (October 2022, ACM Transactions on Design Automation of Electronic Systems)

   Graph application workloads are dominated by random memory accesses with poor locality. To tackle the irregular and sparse nature of computation, ReRAM-based Processing-in-Memory (PIM) architectures have been proposed recently. Most of these ReRAM architecture designs have focused on mapping graph computations into a set of multiply-and-accumulate (MAC) operations. ReRAMs also offer a key advantage in reducing memory latency between cores and memory by allowing for processing-in-memory (PIM). However, when implemented on a ReRAM-based manycore architecture, graph applications still pose two key challenges – significant storage requirements (particularly due to wasted zero cell storage), and significant amount of on-chip traffic. To tackle these two challenges, in this paper we propose the design of a 3D NoC-enabled ReRAM-based manycore architecture. Our proposed architecture incorporates a novel crossbar-aware node reordering to reduce ReRAM storage requirements. Secondly, its 3D NoC-enabled design reduces on-chip communication latency. Our architecture outperforms the state-of-the-art in ReRAM-based graph acceleration by up to 5x in performance while consuming up to 10.3x less energy for a range of graph inputs and workloads. 

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4. Wave-PIM: Accelerating Wave Simulation Using Processing-in-Memory

   https://doi.org/10.1145/3472456.3472512  

   Hanindhito, Bagus; Li, Ruihao; Gourounas, Dimitrios; Fathi, Arash; Govil, Karan; Trenev, Dimitar; Gerstlauer, Andreas; John, Lizy (August 2021, International Conference on Parallel Processing (ICPP))

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5. PARAG: PIM Architecture for Real-Time Acceleration of GCNs

   https://doi.org/10.1109/HiPC58850.2023.00016  

   Singh, Gian; Kuppannagari, Sanmukh R; Vrudhula, Sarma (December 2023, IEEE)

   Graph Convolutional Networks (GCNs) have successfully incorporated deep learning to graph structures for social network analysis, bio-informatics, etc. The execution pattern of GCNs is a hybrid of graph processing and neural networks which poses unique and significant challenges for hardware implementation. Graph processing involves a large amount of irregular memory access with little computation whereas processing of neural networks involves a large number of operations with regular memory access. Existing graph processing and neural network accelerators are therefore inefficient for computing GCNs. This paper presents Parag, processing in memory (PIM) architecture for GCN computation. It consists of customized logic with minuscule computing units called Neural Processing Elements (NPEs) interfaced to each bank of the DRAM to support parallel graph processing and neural network computation. It utilizes the massive internal parallelism of DRAM to accelerate the GCN execution with high energy efficiency. Simulation results for inference of GCN over standard datasets show a latency and energy reduction by three orders of magnitude over a CPU implementation. When compared to a state-of-the-art PIM architecture, PARAG achieves on an average 4x reduction in latency and 4.23x reduction in the energy-delay-product (EDP). 

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