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Abstract Ramp‐reversal memory has recently been discovered in several insulator‐to‐metal transition materials where a non‐volatile resistance change can be set by repeatedly driving the material partway through the transition. This study uses optical microscopy to track the location and internal structure of accumulated memory as a thin film of VO2is temperature cycled through multiple training subloops. These measurements reveal that the gain of insulator phase fraction between consecutive subloops occurs primarily through front propagation at the insulator‐metal boundaries. By analyzing transition temperature maps, it is found, surprisingly, that the memory is also stored deep inside both insulating and metallic clusters throughout the entire sample, making the metal‐insulator coexistence landscape more rugged. This non‐volatile memory is reset after heating the sample to higher temperatures, as expected. Diffusion of point defects is proposed to account for the observed memory writing and subsequent erasing over the entire sample surface. By spatially mapping the location and character of non‐volatile memory encoding in VO2, this study results enable the targeting of specific local regions in the film where the full insulator‐to‐metal resistivity change can be harnessed in order to maximize the working range of memory elements for conventional and neuromorphic computing applications.
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Tuning the Resistance of a VO 2 Junction by Focused Laser Beam and Atomic Force Microscopy
Abstract Vanadium Dioxide (VO2) is a material that exhibits a phase transition from an insulating state to a metallic state at ≈68 °C. During a temperature cycle consisting of warming followed by cooling, the resistivity of VO2changes by several orders of magnitude over the course of the hysteresis loop. Using a focused laser beam (λ = 532 nm), it is shown that it is possible to optically generate micron‐sized metallic patterns within the insulating phase of a VO2planar junction which can be used to tune, on demand, the resistance of the VO2junction. A resistor network simulation is used to characterize the resulting resistance drops in the devices. These patterns persist while the base temperature is held constant within the hysteretic region while being easily removed totally by simply lowering the base temperature. Surprisingly, it is also observed that the pattern can be partially erased using an atomic force microscope (AFM) tip on the submicron scale. This erasing process can be qualitatively explained by the temperature difference between the VO2surface and the tip which acts as a local cooler. This optical and AFM resistive fine‐tuning offers the possibility of creating controllable synaptic weights between room‐temperature VO2neuristors.
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- Award ID(s):
- 2006192
- PAR ID:
- 10578624
- Publisher / Repository:
- Wiley Blackwell (John Wiley & Sons)
- Date Published:
- Journal Name:
- Advanced Electronic Materials
- Volume:
- 11
- Issue:
- 2
- ISSN:
- 2199-160X
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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