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1. Energy-Efficient Adiabatic MTJ/CMOS-Based CLB for Non-Volatile FPGA

   https://doi.org/10.1109/NANO61778.2024.10628919  

   Nasab, Milad Tanavardi; Yang, Wu; Thapliyal, Himanshu (July 2024, IEEE)

   High flexibility, infinite reconfigurability, and fast design-to-market of FPGAs make them a promising platform for modern applications, such as IoT, medical, and automotive applications. Energy and area limitations are challenging in these applications since many of these applications have limited power and hardware resources. Accordingly, the energy- and area-efficient design of FPGAs is of great importance. In this paper, an adiabatic non-volatile hybrid CMOS/MT J logic-in-memory-based configurable logic block (CLB) has been proposed and compared to its state-of-the-art counterparts. The simulation results show that the proposed design has 98%, 98%, 97%, 97%, 96%, and 92 % lower energy consumption compared to CMOS counterparts for frequencies of 1, 2.5, 5,10,20, and 40 MHz. Also, compared to its adiabatic counterparts, the proposed design has at least 74%, 70%, 69%, 69%, and 46% lower energy consumption for frequencies of 1, 2.5, 5, 10, and 20 MHz, respectively. Also, the proposed design has at least 74% fewer transistors compared to its counterparts. Furthermore, the energy saving of the proposed design for different tunnel magnetoresistance (TMR) is almost consistent. In addition, the proposed design keeps its superiority in energy saving over its counterparts for different power supply voltages. 

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2. EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices

   https://doi.org/10.3390/s21227651  

   Kahleifeh, Zachary; Thapliyal, Himanshu (November 2021, Sensors)

   Internet of Things (IoT) devices have strict energy constraints as they often operate on a battery supply. The cryptographic operations within IoT devices consume substantial energy and are vulnerable to a class of hardware attacks known as side-channel attacks. To reduce the energy consumption and defend against side-channel attacks, we propose combining adiabatic logic and Magnetic Tunnel Junctions to form our novel Energy Efficient-Adiabatic CMOS/MTJ Logic (EE-ACML). EE-ACML is shown to be both low energy and secure when compared to existing CMOS/MTJ architectures. EE-ACML reduces dynamic energy consumption with adiabatic logic, while MTJs reduce the leakage power of a circuit. To show practical functionality and energy savings, we designed one round of PRESENT-80 with the proposed EE-ACML integrated with an adiabatic clock generator. The proposed EE-ACML-based PRESENT-80 showed energy savings of 67.24% at 25 MHz and 86.5% at 100 MHz when compared with a previously proposed CMOS/MTJ circuit. Furthermore, we performed a CPA attack on our proposed design, and the key was kept secret. 

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3. Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

   https://doi.org/10.3390/electronics13071309  

   Yang, Wu; Tanavardi_Nasab, Milad; Thapliyal, Himanshu (April 2024, Electronics)

   Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T. 

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4. MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA

   https://doi.org/10.1109/TVLSI.2025.3539670  

   Nasab, Milad Tanavardi; Thapliyal, Himanshu; Rose, Garrett S (May 2025, IEEE Transactions on Very Large Scale Integration (VLSI) Systems)

   Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart [secured CLB (sCLB) by Zooker et al. (2020)], the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages. 

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5. Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices

   https://doi.org/10.1109/ISVLSI51109.2021.00064  

   Kahleifeh, Zachary; Thapliyal, Himanshu (July 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI))

   The tremendous growth in the number of Internet of Things (IoT) devices has increased focus on the energy efficiency and security of an IoT device. In this paper, we will present a design level, non-volatile adiabatic architecture for low-energy and Correlation Power Analysis (CPA) resistant IoT devices. IoT devices constructed with CMOS integrated circuits suffer from high dynamic energy and leakage power. To solve this, we look at both adiabatic logic and STT-MTJs (Spin Transfer Torque Magnetic Tunnel Junctions) to reduce both dynamic energy and leakage power. Furthermore, CMOS integrated circuits suffer from side-channel leakage making them insecure against power analysis attacks. We again look to adiabatic logic to design secure circuits with uniform power consumption, thus, defending against power analysis attacks. We have developed a hybrid adiabatic-MTJ architecture using two-phase adiabatic logic. We show that hybrid adiabatic-MTJ circuits are both low energy and secure when compared with CMOS circuits. As a case study, we have constructed one round of PRESENT and have shown energy savings of 64.29% at a frequency of 25 MHz. Furthermore, we have performed a correlation power analysis attack on our proposed design and determined that the key was kept hidden. 

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