Lookup-table decoding is fast and distance preserving, making it attractive for near-term quantum computer architectures with small-distance quantum error-correcting codes. In this work, we develop several optimization tools that can potentially reduce the space and time overhead required for flag fault-tolerant quantum error correction (FTQEC) with lookup-table decoding on Calderbank-Shor-Steane (CSS) codes. Our techniques include the compact lookup-table construction, the meet-in-the-middle technique, the adaptive time decoding for flag FTQEC, the classical processing technique for flag information, and the separate - and -counting technique. We evaluate the performance of our tools using numerical simulation of hexagonal color codes of distances 3, 5, 7, and 9 under circuit-level noise. Combining all tools can result in an increase of more than an order of magnitude in the pseudothreshold for the hexagonal color code of distance 9, from to . Published by the American Physical Society2024 
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                    This content will become publicly available on May 1, 2026
                            
                            Fast and Parallelizable Logical Computation with Homological Product Codes
                        
                    
    
            Quantum error correction is necessary to perform large-scale quantum computation but requires extremely large overheads in both space and time. High-rate quantum low-density-parity-check (qLDPC) codes promise a route to reduce qubit numbers, but performing computation while maintaining low space cost has required serialization of operations and extra time costs. In this work, we design fast and parallelizable logical gates for qLDPC codes and demonstrate their utility for key algorithmic subroutines such as the quantum adder. Our gate gadgets utilize transversal logical s between a data qLDPC code and a suitably constructed ancilla code to perform parallel Pauli product measurements (PPMs) on the data logical qubits. For hypergraph product codes, we show that the ancilla can be constructed by simply modifying the base classical codes of the data code, achieving parallel PPMs on a subgrid of the logical qubits with a lower space-time cost than existing schemes for an important class of circuits. Generalizations to 3D and 4D homological product codes further feature fast PPMs in constant depth. While prior work on qLDPC codes has focused on individual logical gates, we initiate the study of fault-tolerant compilation with our expanded set of native qLDPC code operations, constructing algorithmic primitives for preparing -qubit Greenberger-Horne-Zeilinger states and distilling or teleporting magic states with space overhead in and logical cycles, respectively. We further generalize this to key algorithmic subroutines, demonstrating the efficient implementation of quantum adders using parallel operations. Our constructions are naturally compatible with reconfigurable architectures such as neutral atom arrays, paving the way to large-scale quantum computation with low space and time overheads. Published by the American Physical Society2025 
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                            - PAR ID:
- 10608552
- Publisher / Repository:
- American Physical Society
- Date Published:
- Journal Name:
- Physical Review X
- Volume:
- 15
- Issue:
- 2
- ISSN:
- 2160-3308
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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