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This content will become publicly available on April 21, 2026

Title: High-Speed CMOS Silicon Photonic PAM4 Transceiver Front-End Circuits
Growing interconnect bandwidth demand in large datacenters requires energy-efficient optical transceivers that operate with four-level pulse amplitude modulation (PAM4) to enable high per-wavelength data rates. Further increases in bandwidth density is possible by leveraging wavelength-division multiplexing (WDM), which optical link architectures based on silicon photonic microring modulators (MRMs) and drop filters inherently enable. This paper presents high-speed PAM4 transmitter and receiver front-ends implemented in a 28nm CMOS process that are co-designed with these silicon photonic optical devices to enable energy-efficient operation. The transmitter utilizes an optical digital-to-analog converter (DAC) approach with two PAM2 AC-coupled pulsed-cascode high-swing voltage-mode output stages to drive the MRM MSB/LSB segments. A 3.42Vppd output swing is achieved when operating at 80Gb/s PAM4 with an energy efficiency of 3.66pJ/bit. The receiver front-end interfaces with a silicon-germanium avalanche photodiode (APD) and utilizes a low-bandwidth input transimpedance amplifier followed by continuous-time linear equalizer and variable-gain amplifier stages. Biasing the APD to realize a gain of 2 allows for -7dBm optical modulation amplitude (OMA) sensitivity at 56Gb/s PAM4 with a BER=10-4 and an energy efficiency of 1.61pJ/bit. Experimental verification of the full PAM4 transceiver at 50Gb/s operation shows -4.66dBm OMA sensitivity at a BER~4x10-4.  more » « less
Award ID(s):
2314868
PAR ID:
10612820
Author(s) / Creator(s):
; ; ; ; ; ; ; ; ; ; ; ; ; ;
Publisher / Repository:
2025 International VLSI Symposium on Technology, Systems and Applications
Date Published:
Format(s):
Medium: X
Location:
Hsinchu, Taiwan
Sponsoring Org:
National Science Foundation
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