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1. Invited: EDA for Heterogeneous Integration

   Haque, E; Nalla, P; Sudarshan, CC; Yogi, D; Zhang, H; Chakrabarti, C; Chhabria, VA; Harjani, R; Zhang, J; Sapatnekar, SS (June 2025, IEEE)

   The advent of heterogeneous integration (HI) places new demands on EDA tooling. Building large systems requires (1) methods for chiplet disaggregation that map the system to smaller chiplets, working in conjunction with system-technology co-optimization to determine the right design decisions that optimize computation and communication, together with the choice of substrate and chiplet technologies; (2) multiphysics and multiscale analyses that incorporate thermomechanical aspects into performance analysis, ranging from fast machine-learning- driven analyses in early stages to signoff-quality multiphysics-based analysis; (3) physical design techniques for placing and routing chiplets and embedded active/passive elements on and within the substrate, including the design of thermal and power delivery solutions; and (4) underlying infrastructure required to facilitate HI-based design, including the design and characterization of chiplet libraries and the establishment of data formats and standards. This paper overviews these issues and lays out a set of EDA needs for HI designs. 

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2. Essential Building Blocks for Creating an Open-source EDA Project

   https://doi.org/10.1145/3316781.3323477  

   Huang, Tsung-Wei; Lin, Chun-Xun; Guo, Guannan; Wong, Martin D. (June 2019, ACM)
3. Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms

   https://doi.org/10.1109/ICCAD57390.2023.10323760  

   Chiu, Cheng-Hsiang; Lin, Dian-Lun; Huang, Tsung-Wei (October 2023, IEEE)
4. EDA photochemistry: Mechanistic investigations and future opportunities

   https://doi.org/10.1016/j.chempr.2023.06.013  

   Wortman, Alan K.; Stephenson, Corey R.J. (September 2023, Chem)
5. Does logic locking work with EDA Tools

   Han, Zhaokun; Yasin, Muhammad; Rajendran, Jeyavijayan (April 2021, USENIX Security Conference 2021)

   Logic locking is a promising solution against emerging hardware security threats, which entails protecting a Boolean circuit using a “keying” mechanism. The latest and hitherto unbroken logic-locking techniques are based on the “corrupt-and-correct (CAC)” principle, offering provable security against input-output query attacks. However, it remains unclear whether these techniques are susceptible to structural attacks. This paper exploits the properties of integrated circuit (IC) design tools, also termed electronic design automation (EDA) tools, to undermine the security of the CAC techniques. Our proposed attack can break all the CAC techniques, including the unbroken CACrem technique that 40+ hackers taking part in a competition for more than three months could not break. Our attack can break circuits processed with any EDA tools, which is alarming because, until now, none of the EDA tools can render a secure locking solution: logic locking cannot make use of the existing EDA tools. We also provide a security property to ensure resilience against structural attacks. The commonly-used circuits can satisfy this property but only in a few cases where they cannot even defeat brute-force; thus, questions arise on the use of these circuits as benchmarks to evaluate logic locking and other security techniques. 

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