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This paper presents an enhanced closed-form approach for modeling and optimizing high-frequency PCB vias, implemented in Python and validated against industrystandard tools such as ADS and HFSS. The model incorporates resistance alongside inductance and capacitance to capture frequency-dependent losses and integrates non-functional pads (NFPs), demonstrating significant improvements in signal integrity by reducing reflections and enhancing return loss, particularly at 100 GHz. The methodology extends the frequency range of previous models from 100 GHz to 150 GHz, ensuring compatibility with next-generation standards like PCIe Gen 6. Validation results show insertion loss deviations under 3 dB and consistent return loss across the frequency range. The Python-based implementation offers a scalable and efficient solution for multilayer via designs, significantly reducing computational time compared to HFSS. This work provides a robust framework for high-speed PCB via modeling, with applications in academic research and industry, and includes future extensions to model differential signal vias. 

This study shows that placing four NFPs in selective PCB layers significantly improves signal integrity, reducing minimum jitter from 18.28 ps to 12.81 ps and maximum jitter from 27.66 ps to 22.03 ps.