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  1. Transition fault testing is an important component of modern testing for delay defects. Unfortunately, test pattern sets for delay defects tend to be significantly longer than test pattern sets for static defects. In the past, various approaches have been devised to detect static defects during scan shift to reduce test time and increase defect coverage. In this paper, we propose a DFT (Design-For-Test) enhancement to allow delay defects to be detected by stuck-at test patterns during scan shift as well.
    Free, publicly-accessible full text available May 23, 2023
  2. Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.
  3. Abstract Inflorescence architecture in cereal crops directly impacts yield potential through regulation of seed number and harvesting ability. Extensive architectural diversity found in inflorescences of grass species is due to spatial and temporal activity and determinacy of meristems, which control the number and arrangement of branches and flowers, and underlie plasticity. Timing of the floral transition is also intimately associated with inflorescence development and architecture, yet little is known about the intersecting pathways and how they are rewired during development. Here, we show that a single mutation in a gene encoding an AP1/FUL-like MADS-box transcription factor significantly delays flowering time and disrupts multiple levels of meristem determinacy in panicles of the C4 model panicoid grass, Setaria viridis. Previous reports of AP1/FUL-like genes in cereals have revealed extensive functional redundancy, and in panicoid grasses, no associated inflorescence phenotypes have been described. In S. viridis, perturbation of SvFul2, both through chemical mutagenesis and gene editing, converted a normally determinate inflorescence habit to an indeterminate one, and also repressed determinacy in axillary branch and floral meristems. Our analysis of gene networks connected to disruption of SvFul2 identified regulatory hubs at the intersection of floral transition and inflorescence determinacy, providing insights into the optimizationmore »of cereal crop architecture.« less
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  5. Globally, most human caloric intake is from crops that belong to the grass family (Poaceae), including sugarcane (Saccharum spp.), rice (Oryza sativa), maize (or corn, Zea mays), and wheat (Triticum aestivum). The grasses have a unique morphology and inflorescence architecture, and some have also evolved an uncommon photosynthesis pathway that confers drought and heat tolerance, the C4 pathway. Most secondary-level students are unaware of the global value of these crops and are unfamiliar with plant science fundamentals such as grass architecture and the genetic concepts of genotype and phenotype. Green foxtail millet (Setaria viridis) is a model organism for C4 plants and a close relative of globally important grasses, including sugarcane. It is ideal for teaching about grass morphology, the economic value of grasses, and the C4 photosynthetic pathway. This article details a teaching module that uses S. viridis to engage entire classrooms of students in authentic research through a laboratory investigation of grass morphology, growth cycle, and genetics. This module includes protocols and assignments to guide students through the process of growing one generation of S. viridis mutants and reference wild-type plants from seed to seed, taking measurements, making critical observations of mutant phenotypes, and discussing their physiological implications.
  6. Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.
  7. Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, overheating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction— approaching 100% for multiple patterns.