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Creators/Authors contains: "Khalil, Waleed"

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  1. A low-power and compact 3-bit active phase shifter is designed and implemented in a 22 nm FDSOI CMOS process. A modified inverter-based topology, which takes advantage of miller capacitance, is used to create a compact and low-power solution, resulting in 10 and 90 x reduction in the power and chip area, respectively, for a given phase shift, compared to the standard inverter-based topology. At the same time, the proposed phase shifter exhibits less sensitivity to device mismatch. The proposed design measures 0.004 mm2, consumes 1.8 mW, and delivers up to 65°of phase shift with RMS phase and amplitude error of 3.85°and ±0.34 dB, respectively. The measured die-to-die variation is also confined to ±6.2°, which is 10% of the full range 
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  2. True Random Number Generators (TRNGs) are a key building block in cryptography. In order to obtain random outputs, the TRNG must produce sufficient noise such that the probability of overcoming any offsets caused by on-die variations between devices, which are inescapable in CMOS processes, is high. In this paper, we analyze the metastable latch based TRNG design with regards to relative device strength, type, and size to determine the tradeoffs in robustness to offsets, bit-rate, and power. 
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