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Title: A 2.4 GHz low-power and compact 3-bit active phase shifter utilizing miller capacitance
A low-power and compact 3-bit active phase shifter is designed and implemented in a 22 nm FDSOI CMOS process. A modified inverter-based topology, which takes advantage of miller capacitance, is used to create a compact and low-power solution, resulting in 10 and 90 x reduction in the power and chip area, respectively, for a given phase shift, compared to the standard inverter-based topology. At the same time, the proposed phase shifter exhibits less sensitivity to device mismatch. The proposed design measures 0.004 mm2, consumes 1.8 mW, and delivers up to 65°of phase shift with RMS phase and amplitude error of 3.85°and ±0.34 dB, respectively. The measured die-to-die variation is also confined to ±6.2°, which is 10% of the full range  more » « less
Award ID(s):
2029461
PAR ID:
10494397
Author(s) / Creator(s):
; ; ; ;
Publisher / Repository:
ELSEVIER
Date Published:
Journal Name:
Microelectronics Journal
Volume:
140
Issue:
C
ISSN:
0026-2692
Page Range / eLocation ID:
105914
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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