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Two-dimensional (2D) molybdenum disulfide (MoS2) holds immense promise for next-generation electronic applications. However, the role of contact deposition at the metal/semiconductor interface remains a critical factor influencing device performance. This study investigates the impact of different metal deposition techniques, specifically electron-beam evaporation and sputtering, for depositing Cu, Pd, Bi, Sn, Pt, and In. Utilizing Raman spectroscopy with backside illumination, we observe changes at the buried metal/1L MoS2 interface after metal deposition. Sputter deposition causes more damage to monolayer MoS2 than electron-beam evaporation, as indicated by partial or complete disappearance of first-order E′(Γ)α and A′1(Γ)α Raman modes post-deposition. We correlated the degree of damage from sputtered atoms to the cohesive energies of the sputtered material. Through fabrication and testing of field-effect transistors, we demonstrate that electron-beam evaporated Sn/Au contacts exhibit superior performance including reduced contact resistance (~12×), enhanced mobility (~4.3×), and lower subthreshold slope (~0.6×) compared to their sputtered counterparts. Our findings underscore the importance of contact fabrication methods for optimizing the performance of 2D MoS2 devices and the value of Raman spectroscopy with backside illumination for gaining insight into contact performance. 

The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%. 

Polymer composites with small amount of CNTs (< 5 wt%) have been studied as a light-weight wear-resistant material with low friction, among other applications, but their modulus improvement often plateaus or diminishes with increasing CNT fraction due to agglomeration. Here, polymer nanocomposites were fabricated with randomly oriented or aligned CNTs across their volume (up to 5 mm length) by CNT surface diazotization and by static magnetic field application (400 G for 40 min). With the improved CNT dispersion and thus less agglomeration, the reduced moduli of PNCs stayed improved with addition of up to 1 vol% (or 1.3 wt%) of CNTs. In this work, the PNCs with randomly oriented CNTs exhibited higher stiffness than the PNCs with magnetically aligned and assembled CNTs, indicating again the negative effect of CNT agglomeration on stiffness. In future, other CNT structuring methods with controlled inter-CNT contacts will be conducted to dissociate alignment from local agglomeration of CNTs and thus to simultaneously improve hardness and modulus of PNCs with small CNT addition.