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Power semiconductor devices are utilized as solid-state switches in power electronics systems, and their overarching design target is to minimize the conduction and switching losses. However, the unipolar figure-of-merit (FOM) commonly used for power device optimization does not directly capture the switching loss. In this Perspective paper, we explore three interdependent open questions for unipolar power devices based on a variety of wide bandgap (WBG) and ultra-wide bandgap (UWBG) materials: (1) What is the appropriate switching FOM for device benchmarking and optimization? (2) What is the optimal drift layer design for the total loss minimization? (3) How does the device power loss compare between WBG and UWBG materials? This paper starts from an overview of switching FOMs proposed in the literature. We then dive into the drift region optimization in 1D vertical devices based on a hard-switching FOM. The punch-through design is found to be optimal for minimizing the hard-switching FOM, with reduced doping concentration and thickness compared to the conventional designs optimized for static FOM. Moreover, we analyze the minimal power loss density for target voltage and frequency, which provides an essential reference for developing device- and package-level thermal management. Overall, this paper underscores the importance of considering switching performance early in power device optimization and emphasizes the inevitable higher density of power loss in WBG and UWBG devices despite their superior performance. Knowledge gaps and research opportunities in the relevant field are also discussed. 

GaN-on-GaN vertical diode is a promising device for next-generation power electronics. Its breakdown voltage (BV) is limited by edge termination designs such as guard rings. The design space of guard rings is huge and it is difficult to optimize manually. In this paper, we propose an effective inverse design strategy to co-optimize BV and (V F Q) −1 , where BV, V F , and Q are the breakdown voltage, forward voltage, and reserve capacitive charge of the diode, respectively. Using rapid Technology Computer-Aided-Design (TCAD) simulations, neural network (NN), and Pareto front generation, a GaN-on-GaN diode is optimized within 24 hours. We can obtain structures with 200V higher BV at medium (V F Q) −1 or find a nearly ideal BV structure with 25% higher BV 2 /R on compared to the best randomly generated TCAD data. 

Multidimensional power devices can achieve performance beyond conventional limits by deploying charge‐balanced p‐n junctions. A key obstacle to developing such devices in many wide‐bandgap (WBG) and ultra‐wide bandgap (UWBG) semiconductors is the difficulty of native p‐type doping. Here the WBG nickel oxide (NiO) as an alternative p‐type material is investigated. The acceptor concentration (N_A) in NiO is modulated by oxygen partial pressure during magnetron sputtering and characterized using a p‐n⁺heterojunction diode fabricated on gallium oxide (Ga₂O₃) substrate. Capacitance and breakdown measurements reveal a tunableN_Afrom < 10¹⁸ cm⁻³to 2×10¹⁸ cm⁻³with the practical breakdown field (E_B) of 3.8 to 6.3 MV cm⁻¹. ThisN_Arange allows for charge balance to n‐type region with reasonable process latitude, andE_Bis high enough to pair with many WBG and UWBG semiconductors. The extractedN_Ais then used to design a multidimensional Ga₂O₃diode with NiO field‐modulation structure. The diodes fabricated with two differentN_Aboth achieve 8000 V breakdown voltage and 4.7 MV cm⁻¹average electric field. This field is over three times higher than the best report in prior multi‐kilovolt lateral devices. These results show the promise of p‐type NiO for pushing the performance limits of power devices. 

Edge termination is the enabling building block of power devices to exploit the high breakdown field of wide bandgap (WBG) and ultra-wide bandgap (UWBG) semiconductors. This work presents a heterogeneous junction termination extension (JTE) based on p-type nickel oxide (NiO) for gallium oxide (Ga2O3) devices. Distinct from prior JTEs usually made by implantation or etch, this NiO JTE is deposited on the surface of Ga2O3 by magnetron sputtering. The JTE consists of multiple NiO layers with various lengths to allow for a graded decrease in effective charge density away from the device active region. Moreover, this surface JTE has broad design window and process latitude, and its efficiency is drift-layer agnostic. The physics of this NiO JTE is validated by experimental applications into NiO/Ga2O3 p–n diodes fabricated on two Ga2O3 wafers with different doping concentrations. The JTE enables a breakdown voltage over 3.2 kV and a consistent parallel-plate junction field of 4.2 MV/cm in both devices, rendering a power figure of merit of 2.5–2.7 GW/cm2. These results show the great promise of the deposited JTE as a flexible, near ideal edge termination for WBG and UWBG devices, particularly those lacking high-quality homojunctions. 

This work demonstrates a novel junction termination extension (JTE) with a graded charge profile for vertical GaN p-n diodes. The fabrication of this JTE obviates GaN etch and requires only a single-step implantation. A bi-layer photoresist is used to produce an ultra-small bevel angle (~0.1°) at the sidewall of a dielectric layer. This tapered dielectric layer is then used as the implantation mask to produce a graded charge profile in p-GaN. The fabricated GaN p-n diodes show a breakdown voltage ( BV ) of 1.7 kV (83% of the parallel-plane limit) with positive temperature coefficient, as well as a high avalanche current density over 1100 A/cm 2 at BV in the unclamped inductive switching test. This robust avalanche is ascribed to the migration of the major impact ionization location from the JTE edge to the main junction. This single-implant, efficient, avalanche-capable JTE can potentially become a building block of many vertical GaN devices, and its fabrication technique has wide device and material applicability.