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In-memory computing represents an effective method for modeling complex physical systems that are typically challenging for conventional computing architectures but has been hindered by issues such as reading noise and writing variability that restrict scalability, accuracy, and precision in high-performance computations. We propose and demonstrate a circuit architecture and programming protocol that converts the analog computing result to digital at the last step and enables low-precision analog devices to perform high-precision computing. We use a weighted sum of multiple devices to represent one number, in which subsequently programmed devices are used to compensate for preceding programming errors. With a memristor system-on-chip, we experimentally demonstrate high-precision solutions for multiple scientific computing tasks while maintaining a substantial power efficiency advantage over conventional digital approaches.
Free, publicly-accessible full text available February 23, 2025 -
Progress in hardware and algorithms for artificial intelligence (AI) has ushered in large machine learning models and various applications impacting our everyday lives. However, today's AI, mainly artificial neural networks, still cannot compete with human brains because of two major issues: the high energy consumption of the hardware running AI models and the lack of ability to generalize knowledge and self-adapt to changes. Neuromorphic systems built upon emerging devices, for instance, memristors, provide a promising path to address these issues. Although innovative memristor devices and circuit designs have been proposed for neuromorphic computing and applied to different proof-of-concept applications, there is still a long way to go to build large-scale low-power memristor-based neuromorphic systems that can bridge the gap between AI and biological brains. This Perspective summarizes the progress and challenges from memristor devices to neuromorphic systems and proposes possible directions for neuromorphic system implementation based on memristive devices.more » « less
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Large remnant polarization and great reliability characteristics in W/HZO/W ferroelectric capacitorsIn this work, the effect of rapid thermal annealing (RTA) temperature on the ferroelectric polarization in zirconium-doped hafnium oxide (HZO) was studied. To maximize remnant polarization (2P r ), in-plane tensile stress was induced by tungsten electrodes under optimal RTA temperatures. We observed an increase in 2P r with RTA temperature, likely due to an increased proportion of the polar ferroelectric phase in HZO. The HZO capacitors annealed at 400°C did not exhibit any ferroelectric behavior, whereas the HZO capacitors annealed at 800°C became highly leaky and shorted for voltages above 1 V. On the other hand, annealing at 700 °C produced HZO capacitors with a record-high 2P r of ∼ 64 μ C cm −2 at a relatively high frequency of 111 kHz. These ferroelectric capacitors have also demonstrated impressive endurance and retention characteristics, which will greatly benefit neuromorphic computing applications.more » « less
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Abstract A diffusive memristor is a promising building block for brain‐inspired computing hardware. However, the randomness in the device relaxation dynamics limits the wide‐range adoption of diffusive memristors in large arrays. In this work, the device stack is engineered to achieve a much‐improved uniformity in the relaxation time (standard deviation σ reduced from ≈12 to ≈0.32 ms). The memristor is further connected with a resistor or a capacitor and the relaxation time is tuned between 1.13 µs and 1.25 ms, ranging from three orders of magnitude. The hierarchy of time surfaces (HOTS) algorithm, to utilize the tunable and uniform relaxation behavior for spike generation, is implemented. An accuracy of 77.3% is achieved in recognizing moving objects in the neuromorphic MNIST (N‐MNIST) dataset. The work paves the way for building emerging neuromorphic computing hardware systems with ultralow power consumption.
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Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN 1+x /Ta 2 O 5 /TaN 1+x /Pd layers that could achieve a NL of 3 × 10 5 , which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta 2 O 5 /Ru based memristor on top of the proposed selector.more » « less