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  1. In this work, the effect of rapid thermal annealing (RTA) temperature on the ferroelectric polarization in zirconium-doped hafnium oxide (HZO) was studied. To maximize remnant polarization (2P r ), in-plane tensile stress was induced by tungsten electrodes under optimal RTA temperatures. We observed an increase in 2P r with RTA temperature, likely due to an increased proportion of the polar ferroelectric phase in HZO. The HZO capacitors annealed at 400°C did not exhibit any ferroelectric behavior, whereas the HZO capacitors annealed at 800°C became highly leaky and shorted for voltages above 1 V. On the other hand, annealing at 700 °C produced HZO capacitors with a record-high 2P r of ∼ 64 μ C cm −2  at a relatively high frequency of 111 kHz. These ferroelectric capacitors have also demonstrated impressive endurance and retention characteristics, which will greatly benefit neuromorphic computing applications.
    Free, publicly-accessible full text available August 25, 2023
  2. Free, publicly-accessible full text available August 29, 2023
  3. Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN 1+x /Ta 2 O 5 /TaN 1+x /Pd layers that could achieve a NL of 3 × 10 5 , which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta 2 O 5 /Ru based memristor on top of the proposed selector.
  4. A highly reliable memristive device based on tantalum‐doped silicon oxide is reported, which exhibits high uniformity, robust endurance (≈1 × 109 cycles), fast switching speed, long retention, and analog conductance modulation. Devices with junction areas ranging from microscale to as small as 60 × 15 nm2 are fabricated and electrically characterized. ON‐/OFF‐ conductance and reset current show weak area dependence when the device is relatively large, and they become proportional to the device area when further scaled down. Two‐layer devices with repeatable switching behavior are achieved. The current study shows the potentials of Ta:SiO2‐based 3D vertical devices for memory and computing applications. It also suggests that doping of the switching layer is an efficient approach to engineer the performance of memristive devices.