Sneak path current is a fundamental issue and a major roadblock to the wide application of memristor crossbar arrays. Traditional selectors such as transistors compromise the 2D scalability and 3D stack‐ability of the array, while emerging selectors with highly nonlinear current–voltage relations contradict the requirement of a linear current–voltage relation for efficient multiplication by directly using Ohm's law. Herein, the concept of a timing selector is proposed and demonstrated, which addresses the sneak path issue with a voltage‐dependent delay time of its transient switching behavior, while preserving a linear current–voltage relationship for computation. Crossbar arrays with silver‐based diffusive memristors as the timing selectors are built and the operation principle and operational windows are experimentally demonstrated. The timing selector enables large memristor crossbar arrays that can be used to solve large‐dimension real‐world problems in machine intelligence and neuromorphic computing.
Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration
Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN 1+x /Ta 2 O 5 /TaN 1+x /Pd layers that could achieve a NL of 3 × 10 5 , which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta 2 O 5 /Ru based memristor on top of the proposed selector.
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- Award ID(s):
- 2023752
- PAR ID:
- 10354309
- Date Published:
- Journal Name:
- Frontiers in Nanotechnology
- Volume:
- 3
- ISSN:
- 2673-3013
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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