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Modern transistors such as FinFETs and gate-all-around FETs (GAAFETs) suffer from excessive heat confinement due to their small size and three-dimensional geometries, with limited paths to the thermal ambient. This results in device self-heating, which can reduce speed, increase leakage, and accelerate aging. This paper characterizes the temperature for both the 7nm FinFET and 5nm GAAFET sub-structures and analyzes its impact on circuit performance (delay and power) and reliability (bias temperature instability, hot carrier injection, and electromigration). On average, logic gates in a circuit heat up by 12K for 7nm SOI FinFET and by 17K for 5nm GAAFET designs. This rise in temperature accelerates delay degradation due to bias temperature instability and hot carrier injection by up to 25% in FinFET and 39% in GAAFET designs, and also degrades the electromigration-induced time to failure of wires by up to 38% in SOI FinFET and 45% in GAAFET technologies. 

This paper studies the impact of hot carrier injection and bias temperature instability on a mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the reset line of the phase detector, degrading sensitivity to input phase differences. Aging also increases threshold voltage mismatch in the charge pump, causing the control voltage of the voltage-controlled delay line to drift, reducing the acquisition time. Numerical results on a 45nm CMOS process are presented.