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Cu3Sn, a well-known intermetallic compound with a high melting temperature and thermal stability, has found numerous applications in microelectronics, 3D printing, and catalysis. However, the relationship between the material's thermal conductivity anisotropy and its complex anti-phase boundary superstructure is not well understood. Here, frequency domain thermoreflectance was used to map the thermal conductivity variation across the surface of arc-melted polycrystalline Cu3Sn. Complementary electron backscatter diffraction and transmission electron microscopy revealed the thermal conductivity in the principal a, b, and c orientations to be 57.6, 58.9, and 67.2 W/m-K, respectively. Density functional theory calculations for several Cu3Sn superstructures helped examine thermodynamic stability factors and evaluate the direction-resolved electron transport properties in the relaxation time approximation. The analysis of computed temperature- and composition-dependent free energies suggests metastability of the known long-period Cu3Sn superstructures while the transport calculations indicate a small directional variation in the thermal conductivity. The ∼15% anisotropy measured and computed in this study is well below previously reported experimental values for samples grown by liquid-phase electroepitaxy.Free, publicly-accessible full text available April 1, 2023
We previously demonstrated how the Sn3Ag4Ti alloy can robustly bond onto silicon via selective laser melting (SLM). By employing this technology, thermal management devices (e.g., micro-channels, vapor chamber evaporators, heat pipes) can be directly printed onto the electronic package (silicon die) without using thermal interface materials. Under immersion two-phase cooling (pool boiling), we compare the performance of three chip cooling methods (conventional heat sink, bare silicon die and additively manufactured metal micro-fins) under high heat flux conditions (100 W/cm2 ). Heat transfer simulations show a significant reduction in the chip temperature for the silicon micro-fins. Reduction of the chip operating temperature or increase in clock speed are some of the advantages of this technology, which results from the elimination of thermal interface materials in the electronic package. Performance and reliability aspects of this technology are discussed through experiments and computational models.