Recent commercial efforts have reestablished the benefits of cooling server modules using direct liquid cooling (DLC) technology. The primary drivers behind this technology are the increase in chip densities and the absolute need to reduce the overall data center power usage. In DLC technology, a cold plate is situated on top of the chip with thermal interface material between the chip and the cold plate. The low thermal resistance path facilitates the use of warm water which helps data centers in replacing the chilled water system by a water side economizer utilizing ambient temperature. This work describes the effort to leverage DLC by employing microchannel cold plates to cool multi-chip modules. The primary objective of this work is to build a sophisticated test rig to characterize the flow and thermal performance of a microchannel cold plate for cooling a two-die chip. This study highlights the challenges of building an experimental setup which simulates a two-die chip package and the approaches taken to overcome the challenges. A parallel channel cold plate is used to benchmark the performance. Tests were conducted for a set of independent variables like flow rate, input power to dice, coolant temperature, flow direction and TIM resistance. The results are presented as PQ curves, specific thermal resistance curves and case temperature distribution reflecting the effect of changing the input variables.
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Additive Laser Metal Deposition Onto Silicon for Enhanced Microelectronics Cooling
We previously demonstrated how the Sn3Ag4Ti alloy can robustly bond onto silicon via selective laser melting (SLM). By employing this technology, thermal management devices (e.g., micro-channels, vapor chamber evaporators, heat pipes) can be directly printed onto the electronic package (silicon die) without using thermal interface materials. Under immersion two-phase cooling (pool boiling), we compare the performance of three chip cooling methods (conventional heat sink, bare silicon die and additively manufactured metal micro-fins) under high heat flux conditions (100 W/cm2 ). Heat transfer simulations show a significant reduction in the chip temperature for the silicon micro-fins. Reduction of the chip operating temperature or increase in clock speed are some of the advantages of this technology, which results from the elimination of thermal interface materials in the electronic package. Performance and reliability aspects of this technology are discussed through experiments and computational models.
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- NSF-PAR ID:
- 10132348
- Date Published:
- Journal Name:
- 2019 IEEE 69th Electronic Components and Technology Conference (ECTC)
- Page Range / eLocation ID:
- 1970 to 1976
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/ECTC.2019.00302
