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Abstract Objective.Advances in brain–machine interfaces (BMIs) can potentially improve the quality of life of millions of users with spinal cord injury or other neurological disorders by allowing them to interact with the physical environment at their will.Approach.To reduce the power consumption of the brain-implanted interface, this article presents the first hardware realization of anin vivointention-aware interface via brain-state estimation.Main Results.It is shown that incorporating brain-state estimation reduces thein vivopower consumption and reduces total energy dissipation by over 1.8× compared to those of the current systems, enabling longer better life for implanted circuits. The synthesized application-specific integrated circuit (ASIC) of the designed intention-aware multi-unit spike detection system in a standard 180 nm CMOS process occupies 0.03 mm²of silicon area and consumes 0.63 µW of power per channel, which is the least power consumption among the currentin vivoASIC realizations.Significance.The proposed interface is the first practical approach towards realizing asynchronous BMIs while reducing the power consumption of the BMI interface and enhancing neural decoding performance compared to those of the conventional synchronous BMIs. 

Intracortical brain computer interfaces (iBCIs) utilizing extracellular recordings mainly employ in vivo signal processing application-specific integrated circuits (ASICs) to detect action potentials (spikes). Conventionally, “brain-switches” based on spiking activity have been employed to realize asynchronous (self-paced) iBCIs, estimating when the user involves in the underlying BCI task. Several studies have demonstrated that local field potentials (LFPs) can effectively replace action potentials, drastically reducing the power consumption and processing requirements of in vivo ASICs. This article presents the first LFP-based brain-switch design and implementation using gated recurrent neural networks (RNNs). Compared to the previously reported brain-switches, our design requires no exhaustive learning phase for the estimation of optimal recording channels or frequency band selection, making it more applicable to practical asynchronous iBCIs. The synthesized ASIC of the designed in vivo LFP-based feature extraction unit, in a standard 180-nm CMOS process, occupies only 0.09 mm^2 of silicon area, and the post place-and-route synthesis results indicate that it consumes 91.87 nW of power while operating at 2 kHz. Compared to the previously published ASICs, the proposed LFP-based brain-switch consumes the least power for in vivo digital signal processing and achieves comparable state estimation performance to that of spike-based brain-switches. 

Conventional in vivo neural signal processing involves extracting spiking activity within the recorded signals from an ensemble of neurons and transmitting only spike counts over an adequate interval. However, for brain-computer interface (BCI) applications utilizing continuous local field potentials (LFPs) for cognitive decoding, the volume of neural data to be transmitted to a computer imposes relatively high data rate requirements. This is particularly true for BCIs employing high-density intracortical recordings with hundreds or thousands of electrodes. This article introduces the first autoencoder-based compression digital circuit for the efficient transmission of LFP neural signals. Various algorithmic and architectural-level optimizations are implemented to significantly reduce the computational complexity and memory requirements of the designed in vivo compression circuit. This circuit employs an autoencoder-based neural network, providing a robust signal reconstruction. The application-specific integrated circuit (ASIC) of the in vivo compression logic occupies the smallest silicon area and consumes the lowest power among the reported state-of-the-art compression ASICs. Additionally, it offers a higher compression rate and a superior signal-to-noise and distortion ratio.