skip to main content
Explore Scholarly Publications and Datasets in the NSF-PAR

  • Home
  • Search Results
  • Page 1 of 1

Search for: All records

Award ID contains: 2011236

Note: When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external site maintained by the publisher. Some full text articles may not yet be available without a charge during the embargo (administrative interval).
What is a DOI Number?

Some links on this page may take you to non-federal websites. Their policies may differ from this site.

  1. ; ; ; ( , Proceedings of the ASPDAC Asia and South Pacific Design Automation Conference)
    Free, publicly-accessible full text available January 17, 2023
  2. ; ; ; ; ( , IEEE International Symposium on Hardware Oriented Security and Trust (HOST))
    Free, publicly-accessible full text available December 12, 2022
  3. ; ; ; ; ( , ACM Transactions on Embedded Computing Systems)
    Hardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on the resource-constrained embedded devices. While accelerators facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in their on-chip and off-chip memories, where millions of DNN weights are held. The use of emerging Non-Volatile Memories (NVM) further exposes DNN accelerators to a non-negligible rate of permanent defects due to immature fabrication, limited endurance, and aging. To tolerate defects in NVM-based DNN accelerators, previous work either requires extra redundancy in hardware or performs defect-aware retraining, imposing significant overhead. In comparison, this paper proposes amore »set of algorithms that exploit the flexibility in setting the fault-free bits in weight memory to effectively approximate weight values, so as to mitigate defect-induced accuracy drop. These algorithms can be applied as a one-step solution when loading the weights to embedded devices. They only require trivial hardware support and impose negligible run-time overhead. Experiments on popular DNN models show that the proposed techniques successfully boost inference accuracy even in the face of elevated defect rates in the weight memory.« less
    Free, publicly-accessible full text available October 31, 2022
  4. ; ( , IEEE Transactions on Neural Networks and Learning Systems)
    Full Text Available 
  5. ; ; ( , IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020)
    Accepted Manuscript Full Text Available
  6. ; ; ; ; ; ; ; ( , the 23rd International Conference on Medical Image Computing and Computer Assisted Intervention (MICCAI))
    Accepted Manuscript Full Text Available
  7. ; ; ; ; ( , IEEE/ACM Design Automation Conference (DAC))
    ReRAM-based neural network accelerator is a promising solution to handle the memory- and computation-intensive deep learning workloads. However, it suffers from unique device errors. These errors can accumulate to massive levels during the run time and cause significant accuracy drop. It is crucial to obtain its fault status in real-time before any proper repair mechanism can be applied. However, calibrating such statistical information is non-trivial because of the need of a large number of test patterns, long test time, and high test coverage considering that complex errors may appear in million-to-billion weight parameters. In this paper, we leverage the conceptmore »of corner data that can significantly confuse the decision making of neural network model, as well as the training algorithm, to generate only a small set of test patterns that is tuned to be sensitive to different levels of error accumulation and accuracy loss. Experimental results show that our method can quickly and correctly report the fault status of a running accelerator, outperforming existing solutions in both detection efficiency and cost.« less
    Accepted Manuscript Full Text Available