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  1. Free, publicly-accessible full text available September 1, 2024
  2. With the increasing complexity of highly integrated system on chips (SoCs), the power management system (PMS) is required to provide several power supplies efficiently for individual blocks. This paper presents a single-inductor multiple outputs (SIMO) an inductor-first hybrid converter that generates three outputs between 0.4V and 1.6V from a 1.8V input. The proposed multiple-output hybrid power stage can improve the conversion efficiency by reducing inductor current while extending the output voltage range compared with the existing hybrid topologies. In addition, the proposed converter employs an on-chip switched-capacitor power stage (SCPS) with a dual switching frequency technique, resulting in a fast response time, low cross-regulation, and reduced number of on-chip pads. Measurement results show that the converter achieves a peak efficiency of 87.5% with a maximum output current of 450mA. The converter is integrated with a fast voltage regulation loop with a 500MHz system clock to achieve less than 0.01mA/mV cross-regulation and a maximum 20mV overshoot at full-load transient response. The design is fabricated in the standard 180nm CMOS technology 
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  3. This paper presents a low phase noise 28 GHz voltage-controlled oscillator (VCO) using a transformer-based active impedance converter to enhance the quality factor (Q) of the capacitor in the resonator. The active impedance converter can enhance the Q of a capacitor bank and varactor by 25-40% across the VCO’s tuning range. The proposed VCO is fabricated using the proposed transformer-based Q-enhancement impedance converter in a standard 65 nm CMOS process. The VCO achieves a 15.9% measured fractional frequency tuning range and phase noise of −107.6 dBc/Hz at 1 MHz offset from 28 GHz oscillation frequency while occupying only 0.05 mm2 area (200 μm × 250 μm). The VCO consumes 5.1 mW power, resulting in an excellent figure-of-merit (FoM) of 189.4 dBc/Hz and a figure-of-merit-with-area (FoMA) of 202.8 dBc/Hz. 
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  4. We present a low phase noise four-core triple-band voltage controlled-oscillator (VCO) with reconfigurable oscillator cores and multi-mode resonator. By activation/deactivation of oscillator cores and change of resonator impedance in three modes of operations, the proposed VCO provides complete freedom in selecting the resonance frequency for three operation bands in the mm-wave range. Compared to VCOs using switch-capacitor-bank for multi-band operation, the proposed VCO does not use any series switches with passive components in the resonator to provide a low phase noise in all three bands of operation. As a proof of concept, the proposed four-core triple-band VCO is implemented in a 65 nm CMOS process using four class-D oscillators with tail switches and a compact high-Q triple-mode resonator. The VCO oscillation frequencies center at 19, 28, and 38 GHz while providing good phase noise and low power consumption in all bands. Measured results show the total frequency tuning range (FTR) of 38.5% while the PN at 1MHz offset varies from -100.3 dBc/Hz to -106.06dBc/Hz resulting in an excellent FoMT of 199.8 dBc/Hz. 
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  5. In the baseband time delay (TD) elements used for delay compensation in discrete-time beamformers, phase interpolator (PI) plays a crucial role as the resolution of the PI defines the delay resolution of the TD. In this paper, we present a process and temperature invariant high-resolution and highly linear low-power PI. The proposed PI uses current integration which generates an adaptable constant slope-and-swing ramp signal to achieve low power. By switched-capacitor bias generation, the PI linearity is enhanced with 0.2 LSB DNL and 0.3 LSB INL, respectively. The 7-bit PI is realized in 65nm CMOS technology can generate the full range delay with a resolution of 8psec with the input of 1GHz. The PI consumes a power of 345μW and occupies an active area of 0.021mm2. Keywords—Ramp-rate tracking, constant slope-and-swing, phase interpolator, ramp-based, baseband time delay 
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  6. Optimizing expensive to evaluate black-box functions over an input space consisting of all permutations of d objects is an important problem with many real-world applications. For example, placement of functional blocks in hardware design to optimize performance via simulations. The overall goal is to minimize the number of function evaluations to find high-performing permutations. The key challenge in solving this problem using the Bayesian optimization (BO) framework is to trade-off the complexity of statistical model and tractability of acquisition function optimization. In this paper, we propose and evaluate two algorithms for BO over Permutation Spaces (BOPS). First, BOPS-T employs Gaussian process (GP) surrogate model with Kendall kernels and a Tractable acquisition function optimization approach to select the sequence of permutations for evaluation. Second, BOPS-H employs GP surrogate model with Mallow kernels and a Heuristic search approach to optimize the acquisition function. We theoretically analyze the performance of BOPS-T to show that their regret grows sub-linearly. Our experiments on multiple synthetic and real-world benchmarks show that both BOPS-T and BOPS-H perform better than the state-of-the-art BO algorithm for combinatorial spaces. To drive future research on this important problem, we make new resources and real-world benchmarks available to the community. 
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  7. Radio frequency interference (RFI) in a devastating problem for high-sensitivity phased arrays. This paper explores a method of mitigating RFI in a receiving array using a combination of true-time delay with a truncated Hadamard projection that can place a wide-band spatial null over the RFI. The operations involved can be performed with analog circuity before sampling for the digital signal processing engine in order to enhance dynamic range. The modified beamformer solution is briefly derived and performance is compared to the existing maximum SINR beamformer using analytical phasor domain models. The results show successful null placement at the expense of control of the main lobe shape and side lobe levels. 
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