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This article presents a back-off efficient power amplifier (PA) for mm-wave 5G and upcoming 6G beamforming phased array transceivers (PATs), incorporating advanced circuit designs and novel implementations in both passive and active components. Conventional back-off efficient PAs in the mm-wave frequency range occupy a large chip area, making it hard to fit them into PATs. To overcome this issue, we propose a compact back-off efficient Doherty PA (DPA) with a common base (CB) structure as the core of the PA and small low-loss passive elements. In addition, the proposed architecture moves the role of the input hybrid coupler to the interstage matching network while maintaining DPA functionality. The interstage matching provides the required phases for the main and auxiliary PAs, power division, and impedance matching. The PA prototype is fabricated in the GlobalFoundries 90-nm BiCMOS (9 HP) process. It achieves a peak gain of 20.4 dB at 28.45 GHz with a 1-dB bandwidth of 4.45 GHz. Under large-signal conditions, it archives >19.5-dBm Psat with >36% PAEsat. Its P1dB at 26, 28, and 30 GHz are 19.4, 19.3, and 19.3 dBm with 38.5%, 37.3%, and 36.8% PAE1 dB, respectively. In the 6-dB power back-off region, it reaches efficiencies of 29.1%, 31.1%, and 29.3% at 26, 28, and 30 GHz, respectively. When tested with the NR-FR2 test model at these frequencies, the PA achieves Pavg of 8.25, 8.45, and 8 dBm, and PAEavg of 13.9%, 14.5%, and 13.7% for a 400 M 1-CC 64-QAM signal, maintaining an rms error vector magnitude (EVMrms) of −25.8, −25.8, and −25.7 dB. In addition, in adjacent channel power ratio (ACPR) tests, the PA achieves −27, −26.2, and −30.8 dBc on the lower side and −28.4, −28.5, and −27.6 dBc on the higher side channels at 26, 28, and 30 GHz, respectivelyNot Available 

This article presents a dual-band power amplifier for 28 and 39 GHz frequency bands based on a new dual-path transformer (DPT). This DPT can provide two optimum inductive values at two different frequency bands to optimally design the matching networks for each band without using any switch circuitries. It operates as the output and input matching networks in a parallel power combiner and divider, respectively. DPT-based PA breaks the trade-off between bandwidth and performance in conventional wideband PAs by separating one whole wideband into two narrow bands providing optimum input and output matchings for each band. The DPT-based PA has two input and two output ports. One set of input and output ports is dedicated to a lower frequency band and the other set of input and outport ports can be used for a higher frequency band. Each output port can drive a separate antenna in a phased array for each frequency band. The proposed PA prototype is fabricated in a 65 nm CMOS process achieving 15.3 and 14.0 dBm of saturated output power in 28 and 39 GHz. The peak efficiency of the PA is 34.1% and 30.2% at 28 and 39 GHz frequency bands. The PA has a measured EVM with 64-QAM modulated signal in both frequency bands showing −25.03 and −25.10 dB in the low and higher frequency bands, respectively. 

This article introduces an innovative four-port dual-path inductor designed to deliver two distinct inductance values to the resonator of a voltage-controlled oscillator (VCO). The switching between the inductor’s two excitation modes, even and odd, is determined by the differential excitation’s input polarity, eliminating the need for a series switch. Thus, the inductor has a high-quality factor ( Q ) in both modes. The inductances in these modes can be independently set based on desired frequencies. This inductance change achieves coarse frequency tuning, while fine-tuning is realized by a conventional 2-bit capacitor bank with a small-size varactor. This inductor is well suited for designing multiband VCOs aimed at widely spaced operation frequency bands. Apart from the inductance change, a particular case of mode-switching capacitor is employed to extend to another frequency band in between the low and middle bands, achieving triple-band oscillation. As a result, this article presents two VCOs designed using the proposed inductor: one in class-D biasing in a 65-nm CMOS process and another with class-B biasing in a 180-nm BiCMOS process. Both VCOs successfully oscillate across three distinct frequency bands, centered at 19, 28, and 36 GHz, while maintaining outstanding phase noise and minimal power consumption. Measurement results show good match with simulation, resulting in a peak figure of merit (FoM) of 185.7 dBc/Hz at 18.5 GHz, and occupy 0.088- mm2 (250 × 350 μ m) area in both processes. 

With the increasing complexity of highly integrated system on chips (SoCs), the power management system (PMS) is required to provide several power supplies efficiently for individual blocks. This paper presents a single-inductor multiple outputs (SIMO) an inductor-first hybrid converter that generates three outputs between 0.4V and 1.6V from a 1.8V input. The proposed multiple-output hybrid power stage can improve the conversion efficiency by reducing inductor current while extending the output voltage range compared with the existing hybrid topologies. In addition, the proposed converter employs an on-chip switched-capacitor power stage (SCPS) with a dual switching frequency technique, resulting in a fast response time, low cross-regulation, and reduced number of on-chip pads. Measurement results show that the converter achieves a peak efficiency of 87.5% with a maximum output current of 450mA. The converter is integrated with a fast voltage regulation loop with a 500MHz system clock to achieve less than 0.01mA/mV cross-regulation and a maximum 20mV overshoot at full-load transient response. The design is fabricated in the standard 180nm CMOS technology 

In the baseband time delay (TD) elements used for delay compensation in discrete-time beamformers, phase interpolator (PI) plays a crucial role as the resolution of the PI defines the delay resolution of the TD. In this paper, we present a process and temperature invariant high-resolution and highly linear low-power PI. The proposed PI uses current integration which generates an adaptable constant slope-and-swing ramp signal to achieve low power. By switched-capacitor bias generation, the PI linearity is enhanced with 0.2 LSB DNL and 0.3 LSB INL, respectively. The 7-bit PI is realized in 65nm CMOS technology can generate the full range delay with a resolution of 8psec with the input of 1GHz. The PI consumes a power of 345μW and occupies an active area of 0.021mm2. Keywords—Ramp-rate tracking, constant slope-and-swing, phase interpolator, ramp-based, baseband time delay