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Abstract Reinforcement learning (RL) relies on Gaussian and sigmoid functions to balance exploration and exploitation, but implementing these functions in hardware typically requires iterative computations, increasing power and circuit complexity. Here, Gaussian‐sigmoid reinforcement transistors (GS‐RTs) are reported that integrate both activation functions into a single device. The transistors feature a vertical n‐p‐i‐p heterojunction stack composed of a‐IGZO and DNTT, with asymmetric source–drain contacts and a parylene interlayer that enables voltage‐tunable transitions between sigmoid, Gaussian, and mixed responses. This architecture emulates the behavior of three transistors in one, reducing the required circuit complexity from dozens of transistors to fewer than a few. The GS‐RT exhibits a peak current of 5.95 µA at V_G= −17 V and supports nonlinear transfer characteristics suited for neuromorphic computing. In a multi‐armed bandit task, GS‐RT‐based RL policies demonstrate 20% faster convergence and 30% higher final reward compared to conventional sigmoid‐ or Gaussian‐based approaches. Extending this advantage further, GS‐RT‐based activation function in deep RL for cartpole balancing significantly outperforms the traditional ReLU‐based activation function in terms of faster learning and tolerance to input perturbations. 

Abstract Probabilistic inference in data-driven models is promising for predicting outputs and associated confidence levels, alleviating risks arising from overconfidence. However, implementing complex computations with minimal devices still remains challenging. Here, utilizing a heterojunction of p- and n-type semiconductors coupled with separate floating-gate configuration, a Gaussian-like memory transistor is proposed, where a programmable Gaussian-like current-voltage response is achieved within a single device. A separate floating-gate structure allows for exquisite control of the Gaussian-like current output to a significant extent through simple programming, with an over 10000 s retention performance and mechanical flexibility. This enables physical evaluation of complex distribution functions with the simplified circuit design and higher parallelism. Successful implementation for localization and obstacle avoidance tasks is demonstrated using Gaussian-like curves produced from Gaussian-like memory transistor. With its ultralow-power consumption, simplified design, and programmable Gaussian-like outputs, our 3-terminal Gaussian-like memory transistor holds potential as a hardware platform for probabilistic inference computing. 

The increasing complexity of deep learning systems has pushed conventional computing technologies to their limits. While the memristor is one of the prevailing technologies for deep learning acceleration, it is only suited for classical learning layers where only two operands, namely weights and inputs, are processed simultaneously. Meanwhile, to improve the computational efficiency of deep learning for emerging applications, a variety of non-traditional layers requiring concurrent processing of many operands are becoming popular. For example, hypernetworks improve their predictive robustness by simultaneously processing weights and inputs against the application context. Two-electrode memristor grids cannot directly map emerging layers’ higher-order multiplicative neural interactions. Addressing this unmet need, we present crossbar processing using dual-gated memtransistors based on two-dimensional semiconductor MoS 2 . Unlike the memristor, the resistance states of memtransistors can be persistently programmed and can be actively controlled by multiple gate electrodes. Thus, the discussed memtransistor crossbar enables several advanced inference architectures beyond a conventional passive crossbar. For example, we show that sneak paths can be effectively suppressed in memtransistor crossbars, whereas they limit size scalability in a passive memristor crossbar. Similarly, exploiting gate terminals to suppress crossbar weights dynamically reduces biasing power by ∼20% in memtransistor crossbars for a fully connected layer of AlexNet. On emerging layers such as hypernetworks, collocating multiple operations within the same crossbar cells reduces operating power by ∼ 15 × on the considered network cases.