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GaN-on-GaN vertical diode is a promising device for next-generation power electronics. Its breakdown voltage (BV) is limited by edge termination designs such as guard rings. The design space of guard rings is huge and it is difficult to optimize manually. In this paper, we propose an effective inverse design strategy to co-optimize BV and (V F Q) −1 , where BV, V F , and Q are the breakdown voltage, forward voltage, and reserve capacitive charge of the diode, respectively. Using rapid Technology Computer-Aided-Design (TCAD) simulations, neural network (NN), and Pareto front generation, a GaN-on-GaN diode is optimized within 24 hours. We can obtain structures with 200V higher BV at medium (V F Q) −1 or find a nearly ideal BV structure with 25% higher BV 2 /R on compared to the best randomly generated TCAD data. 

β-Ga₂O₃is an emerging material and has the potential to revolutionize power electronics due to its ultra-wide-bandgap (UWBG) and lower native substrate cost compared to Silicon Carbide and Gallium Nitride. Sinceβ-Ga₂O₃technology is still not mature, experimental study ofβ-Ga₂O₃is difficult and expensive. Technology-Computer-Aided Design (TCAD) is thus a cost-effective way to study the potentials and limitations ofβ-Ga₂O₃devices. In this paper, TCAD parameters calibrated to experiments are presented. They are used to perform the simulations in heterojunction p-NiO/n-Ga₂O₃diode, Schottky diode, and normally-off Ga₂O₃vertical FinFET. Besides the current-voltage (I-V) simulations, breakdown, capacitance-voltage (C-V), and short-circuit ruggedness simulations with robust setups are discussed. TCAD Sentaurus is used in the simulations but the methodologies can be applied in other simulators easily. This paves the road to performing a holistic study ofβ-Ga₂O₃devices using TCAD.

 

This work demonstrates a novel junction termination extension (JTE) with a graded charge profile for vertical GaN p-n diodes. The fabrication of this JTE obviates GaN etch and requires only a single-step implantation. A bi-layer photoresist is used to produce an ultra-small bevel angle (~0.1°) at the sidewall of a dielectric layer. This tapered dielectric layer is then used as the implantation mask to produce a graded charge profile in p-GaN. The fabricated GaN p-n diodes show a breakdown voltage ( BV ) of 1.7 kV (83% of the parallel-plane limit) with positive temperature coefficient, as well as a high avalanche current density over 1100 A/cm 2 at BV in the unclamped inductive switching test. This robust avalanche is ascribed to the migration of the major impact ionization location from the JTE edge to the main junction. This single-implant, efficient, avalanche-capable JTE can potentially become a building block of many vertical GaN devices, and its fabrication technique has wide device and material applicability. 

In this paper, the short circuit ruggedness of Gallium Oxide (Ga 2 O 3 ) vertical FinFET is studied using Technology Computer-Aided-Design (TCAD) simulations. Ga 2 O 3 is an emerging ultra-wide bandgap material and Ga 2 O 3 vertical FinFET can achieve the normally-off operation for high voltage applications. Ga 2 O 3 has a relatively low thermal conductivity and, thus, it is critical to explore the design space of Ga 2 O 3 vertical FinFETs to achieve an acceptable short-circuit capability for power applications. In this study, appropriate TCAD models and parameters calibrated to experimental data are used. For the first time, the breakdown voltage simulation accuracy of Ga 2 O 3 vertical FinFETs is studied systematically. It is found that a background carrier generation rate between 10 5 cm −3 s −1 and 10 12 cm −3 s −1 is required in simulation to obtain correct results. The calibrated and robust setup is then used to study the short circuit withstand time (SCWT) of an 800 V-rated Ga 2 O 3 vertical FinFET with different inter-fin architectures. It is found that, due to the high thermal resistance in Ga 2 O 3 , to achieve an SCWT >1 μ s, low gate overdrive is needed which increases R on,sp by 66% and that Ga 2 O 3 might melt before the occurrence of thermal runaway. These results provide important guidance for developing rugged Ga 2 O 3 power transistors.