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Abstract Phase‐sensitive integrated photonic devices are highly susceptible to minor manufacturing deviations, resulting in significant performance inconsistencies. This variability has limited the scalability and widespread adoption of these devices. Here, a major advancement is achieved through continuous‐wave (CW) visible light (405 and 520 nm) trimming of plasma‐enhanced chemical vapor deposition (PECVD) silicon‐rich nitride (SRN) waveguides. The demonstrated method achieves precise, bidirectional refractive index tuning with a single laser source in CMOS‐compatible SRN samples with refractive indices of 2.4 and 2.9 (measured at 1550 nm). By utilizing a cost‐effective setup for real‐time resonance tracking in micro‐ring resonators, the resonant wavelength shifts as fine as 10 pm are attained. Additionally, a record red shift of 49.1 nm and a substantial blue shift of 10.6 nm are demonstrated, corresponding to refractive index changes of approximately 0.11 and −2 × 10⁻². The blue and red shifts are both conclusively attributed to thermal annealing. These results highlight SRN's exceptional capability for permanent optical tuning, establishing a foundation for stable, precisely controlled performance in phase‐sensitive integrated photonic devices. 

An energy/area-efficient low-cost broadband linearity enhancement technique using the hybrid of notch-filter and bandpass-filter micro-ring modulators (Hybrid-MRMs) is proposed to achieve higher than 3.01-dB improvement in spurious-free-dynamic-ranges with intermodulation distortions (dSFDRIMD) and 17.9-dB improvement in integral nonlinearity (dINLPP) over a conventional notch-filter MRM (NF-MRM) across a 4.8-dB extinction-ratio full-scale range based on rapid silicon-photonics fabrication results for the emerging applications of various analog and digital optical communication systems. 

This paper adopts advanced monolithic silicon-photonics integrated-circuits manufacturing capabilities to realize system-on-chip photonic-electronic linear-algebra accelerators for self-attention computation in various applications of deep-learning neural networks and Large Language Models. With the features of holistic co-design approaches, optical comb-based broadband modulations, and consecutive matrix-multiplication architecture, the system/circuit/device-level simulations of the proposed accelerator can achieve 2.14-TMAC/s/mm2 computation density and 27.9-fJ/MAC energy efficiency with practical considerations of power/area overhead due to photonic-electronic on-chip conversions, integrations, and calibrations. 

Silicon nitride is widely used in integrated photonics for optical nonlinear wave mixing due to its low optical losses combined with relatively high nonlinear optical properties and a wide‐range transparency window. It is known that a higher concentration of Si in silicon‐rich nitride (SRN) magnifies both the nonlinear response and optical losses, including nonlinear losses. To address the trade‐off, four‐wave mixing (FWM) is implemented in over a hundred SRN waveguides prepared by plasma‐enhanced chemical vapor deposition in a wide range of SRN refractive indices varying between 2.5 and 3.2 (measured in the C‐band). It is determined that SRN with a refractive index of about 3 maximizes the FWM efficiency for continuous‐wave operation, indicating that the refractive index of SRN is indeed a crucial optimization parameter for nonlinear optics applications. The FWM efficiency is limited by large nonlinear optical losses observed in SRN waveguides with indices larger than 2.7, which are not related to two‐photon absorption. Finally, the third‐order susceptibility and the nonlinear refractive index are estimated for multiple SRN refractive indices, and, specifically, the nonlinearities as large as and are estimated in a waveguide with an SRN refractive index of 3.2. 

A system-on-chip (SoC) photonic-electronic linear-algebra accelerator with the features of wavelength-division-multiplexing (WDM) based broadband photodetections and high-dimensional matrix-inversion operations fabricated in advanced monolithic silicon-photonics (M-SiPh) semiconductor process technology is proposed to achieve substantial leaps in computation density and energy efficiency, including realistic considerations of energy/area overhead due to electronic/photonic on-chip conversions, integrations, and calibrations through holistic co-design methodologies to support linear-detection based massive multiple-input multiple-output (MIMO) decoding technology requiring the inversion of channel matrices and other emergent applications limited by linear-algebra computation capacities.