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1. Monolithic Silicon-Photonics Linear-Algebra Accelerators Enabling Next-Gen Massive MIMO

   https://doi.org/10.1109/JLT.2024.3395408  

   Hsueh, Tzu-Chien; Fainman, Yeshaiahu; Lin, Bill (April 2024, Journal of Lightwave Technology)

   Bosco, Gabriella (Ed.)

   A system-on-chip (SoC) photonic-electronic linear-algebra accelerator with the features of wavelength-division-multiplexing (WDM) based broadband photodetections and high-dimensional matrix-inversion operations fabricated in advanced monolithic silicon-photonics (M-SiPh) semiconductor process technology is proposed to achieve substantial leaps in computation density and energy efficiency, including realistic considerations of energy/area overhead due to electronic/photonic on-chip conversions, integrations, and calibrations through holistic co-design methodologies to support linear-detection based massive multiple-input multiple-output (MIMO) decoding technology requiring the inversion of channel matrices and other emergent applications limited by linear-algebra computation capacities. 

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2. Monolithic Silicon‐Photonics Sign‐Sign Dot‐Product Circuits Toward Artificial Intelligence and Multiple‐Input Multiple‐Output Accelerators

   https://doi.org/10.1002/nap2.70063  

   Chaudhury, Sumilak; Johnson, Karl; Alic, Nikola; Lin, Bill; Fainman, Yeshaiahu; Hsueh, Tzu‐Chien (April 2026, Nanophotonics)

   This research leverages advanced monolithic silicon‐photonics integrated‐circuit manufacturing capabilities to realize system‐on‐chip photonic‐computing‐based linear‐algebra accelerators for a wide range of applications in artificial intelligence, machine learning, and multiple‐input multiple‐output wireless technology. With holistic codesign in both photonic and electronic domains, strategic electrical‐to‐optical signal conversion, a differential intensity‐modulation technique, and a dual rail‐to‐rail photodetection architecture, the monolithic photonic‐electronic test chip of a sign‐sign dot‐product accelerator achieves 8.92‐Gb/s/MAC computation throughput with 2.22‐pJ/b/MAC energy consumption for next‐generation large‐scale linear‐algebra computing hardware targeting higher than one TMAC/s/mm^2 computation density with only tens of fJ/MAC energy consumption. 

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3. Model-free optimization and parallel architecture towards monolithic-hybrid-photonic-electronic reservoir computing

   https://doi.org/10.1364/OE.585815  

   Gaur, Prabhav; Gao, Chengkuan; Johnson, Karl; Rubin, Shimon; Fainman, Yeshaiahu; Hsueh, Tzu-Chien (December 2025, Optics Express)

   Physical reservoir computing (PRC) is a recently developed variant of neuromorphic computing, where the output from a nonlinear physical system is utilized to perform various machine learning tasks. In this work, we theoretically analyze the performance of a photonic waveguide mesh (WGM) with electro-optic phase shifters for monolithic-hybrid-photonic-electronic reservoir computing (MHPE RC), where the phase-to-intensity relations in the photonic circuit provide nonlinearity and high dimensionality, while the electronic circuit provides the input and feedback with tunable parameters. First, we numerically demonstrate the efficiency and performance superiority of a parallel architecture comprising fabricated WGM. Next, we present the Lyapunov filtered-minimal redundancy maximal relevance (Lf-mRMR) algorithm, which optimizes the electronic parameters of parallel WGMs by analyzing the Lyapunov exponent and the mutual information between the output of the corresponding WGMs and the required task. The Lf-mRMR algorithm is computationally less complex, substantially improves the performance of MHPE RC, and can tolerate fabrication errors. We present the selective parallel architecture for reservoir computing (SPARC), which, assisted by the Lf-mRMR algorithm, can achieve performance close to convolutional neural networks. Finally, we experimentally employ on-chip silicon photonics with thermo-optical phase shifters and external off-chip digital memory and control unit to validate the advantageous performance of Lf-mRMR-assisted RC. 

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4. Expanding the quantum photonic toolbox in AlGaAsOI

   https://doi.org/10.1063/5.0098984  

   Castro, J. E.; Steiner, T. J.; Thiel, L.; Dinkelacker, A.; McDonald, C.; Pintus, P.; Chang, L.; Bowers, J. E.; Moody, G. (September 2022, APL Photonics)

   Aluminum gallium arsenide-on-insulator (AlGaAsOI) exhibits large [Formula: see text] and [Formula: see text] optical nonlinearities, a wide tunable bandgap, low waveguide propagation loss, and a large thermo-optic coefficient, making it an exciting platform for integrated quantum photonics. With ultrabright sources of quantum light established in AlGaAsOI, the next step is to develop the critical building blocks for chip-scale quantum photonic circuits. Here we expand the quantum photonic toolbox for AlGaAsOI by demonstrating edge couplers, 3 dB splitters, tunable interferometers, and waveguide crossings with performance comparable to or exceeding silicon and silicon-nitride quantum photonic platforms. As a demonstration, we de-multiplex photonic qubits through an unbalanced interferometer, paving the route toward ultra-efficient and high-rate chip-scale demonstrations of photonic quantum computation and information applications. 

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5. A novel approach to interface high-Q Fabry–Pérot resonators with photonic circuits

   https://doi.org/10.1063/5.0174384  

   Cheng, Haotian; Jin, Naijun; Dai, Zhaowei; Xiang, Chao; Guo, Joel; Zhou, Yishu; Diddams, Scott A; Quinlan, Franklyn; Bowers, John; Miller, Owen; et al (November 2023, APL Photonics)

   The unique benefits of Fabry–Pérot resonators as frequency-stable reference cavities and as an efficient interface between atoms and photons make them an indispensable resource for emerging photonic technologies. To bring these performance benefits to next-generation communications, computation, and time-keeping systems, it will be necessary to develop strategies to integrate compact Fabry–Pérot resonators with photonic integrated circuits. In this paper, we demonstrate a novel reflection cancellation circuit that utilizes a numerically optimized multi-port polarization-splitting grating coupler to efficiently interface high-finesse Fabry–Pérot resonators with a silicon photonic circuit. This circuit interface produces a spatial separation of the incident and reflected waves, as required for on-chip Pound–Drever–Hall frequency locking, while also suppressing unwanted back reflections from the Fabry–Pérot resonator. Using inverse design principles, we design and fabricate a polarization-splitting grating coupler that achieves 55% coupling efficiency. This design realizes an insertion loss of 5.8 dB for the circuit interface and more than 9 dB of back reflection suppression, and we demonstrate the versatility of this system by using it to interface several reflective off-chip devices. 

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