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Title: Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM
In this paper, we explore potentials of leveraging spin-based in-memory computing platform as an accelerator for Binary Convolutional Neural Networks (BCNN). Such platform can implement the dominant convolution computation based on presented Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array. The proposed array architecture could simultaneously work as non-volatile memory and a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in conventional logic-in-memory designs. The computed logic output could be also simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. We employ such intrinsic in-memory computing architecture to efficiently process data within memory to greatly reduce power hungry and omit long distance data communication concerning state-of-the-art BCNN hardware.  more » « less
Award ID(s):
Author(s) / Creator(s):
Date Published:
Journal Name:
2017 IEEE International Conference on Computer Design (ICCD)
Page Range / eLocation ID:
609 to 612
Medium: X
Sponsoring Org:
National Science Foundation
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