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1. FPGA-Based Acceleration of Time Series Similarity Prediction: From Cloud to Edge

   https://doi.org/10.1145/3555810  

   Kalantar, Amin; Zimmerman, Zachary; Brisk, Philip (July 2022, ACM Transactions on Reconfigurable Technology and Systems)

   With the proliferation of low-cost sensors and the Internet of Things, the rate of producing data far exceeds the compute and storage capabilities of today’s infrastructure. Much of this data takes the form of time series, and in response, there has been increasing interest in the creation of time series archives in the last decade, along with the development and deployment of novel analysis methods to process the data. The general strategy has been to apply a plurality of similarity search mechanisms to various subsets and subsequences of time series data in order to identify repeated patterns and anomalies; however, the computational demands of these approaches renders them incompatible with today’s power-constrained embedded CPUs. To address this challenge, we present FA-LAMP, an FPGA-accelerated implementation of the Learned Approximate Matrix Profile (LAMP) algorithm, which predicts the correlation between streaming data sampled in real-time and a representative time series dataset used for training. FA-LAMP lends itself as a real-time solution for time series analysis problems such as classification. We present the implementation of FA-LAMP on both edge- and cloud-based prototypes. On the edge devices, FA-LAMP integrates accelerated computation as close as possible to IoT sensors, thereby eliminating the need to transmit and store data in the cloud for posterior analysis. On the cloud-based accelerators, FA-LAMP can execute multiple LAMP models on the same board, allowing simultaneous processing of incoming data from multiple data sources across a network. LAMP employs a Convolutional Neural Network (CNN) for prediction. This work investigates the challenges and limitations of deploying CNNs on FPGAs using the Xilinx Deep Learning Processor Unit (DPU) and the Vitis AI development environment. We expose several technical limitations of the DPU, while providing a mechanism to overcome them by attaching custom IP block accelerators to the architecture. We evaluate FA-LAMP using a low-cost Xilinx Ultra96-V2 FPGA as well as a cloud-based Xilinx Alveo U280 accelerator card and measure their performance against a prototypical LAMP deployment running on a Raspberry Pi 3, an Edge TPU, a GPU, a desktop CPU, and a server-class CPU. In the edge scenario, the Ultra96-V2 FPGA improved performance and energy consumption compared to the Raspberry Pi; in the cloud scenario, the server CPU and GPU outperformed the Alveo U280 accelerator card, while the desktop CPU achieved comparable performance; however, the Alveo card offered an order of magnitude lower energy consumption compared to the other four platforms. Our implementation is publicly available at https://github.com/aminiok1/lamp-alveo. 

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2. Gate reflectometry of single-electron box arrays using calibrated low temperature matching networks

   https://doi.org/10.1038/s41598-022-06727-1  

   Filmer, Matthew J.; Huebner, Matthew; Zirkle, Thomas A.; Jehl, Xavier; Sanquer, Marc; Chisum, Jonathan D.; Orlov, Alexei O.; Snider, Gregory L. (December 2022, Scientific Reports)

   Abstract Sensitive dispersive readouts of single-electron devices (“gate reflectometry”) rely on one-port radio-frequency (RF) reflectometry to read out the state of the sensor. A standard practice in reflectometry measurements is to design an impedance transformer to match the impedance of the load to the characteristic impedance of the transmission line and thus obtain the best sensitivity and signal-to-noise ratio. This is particularly important for measuring large impedances, typical for dispersive readouts of single-electron devices because even a small mismatch will cause a strong signal degradation. When performing RF measurements, a calibration and error correction of the measurement apparatus must be performed in order to remove errors caused by unavoidable non-idealities of the measurement system. Lack of calibration makes optimizing a matching network difficult and ambiguous, and it also prevents a direct quantitative comparison between measurements taken of different devices or on different systems. We propose and demonstrate a simple straightforward method to design and optimize a pi matching network for readouts of devices with large impedance, $$Z \ge 1\hbox {M}\Omega$$ Z ≥ 1 M Ω . It is based on a single low temperature calibrated measurement of an unadjusted network composed of a single L-section followed by a simple calculation to determine a value of the “balancing” capacitor needed to achieve matching conditions for a pi network. We demonstrate that the proposed calibration/error correction technique can be directly applied at low temperature using inexpensive calibration standards. Using proper modeling of the matching networks adjusted for low temperature operation the measurement system can be easily optimized to achieve the best conditions for energy transfer and targeted bandwidth, and can be used for quantitative measurements of the device impedance. In this work we use gate reflectometry to readout the signal generated by arrays of parallel-connected Al-AlOx single-electron boxes. Such arrays can be used as a fast nanoscale voltage sensor for scanning probe applications. We perform measurements of sensitivity and bandwidth for various settings of the matching network connected to arrays and obtain strong agreement with the simulations. 

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3. Sparta: Heat-Budget-Based Scheduling Framework on IoT Edge Systems

   https://doi.org/10.1007/978-3-030-96504-4_2  

   Zhang, M.; Krintz, C.; Wolski, R. (December 2021, Edge Computing)

   Co-location of processing infrastructure and IoT devices at the edge is used to reduce response latency and long-haul network use for IoT applications. As a result, edge clouds for many applications (e.g. agriculture, ecology, and smart city deployments) must operate in remote, unattended, and environmentally harsh settings, introducing new challenges. One key challenge is heat exposure, which can degrade the performance, reliability, and longevity of electronics. For edge clouds, these problems are exacerbated because they increasingly perform complex workloads, such as machine learning, to affect data-driven actuation and control of devices and systems in the environment. The goal of our work is to protect edge clouds from overheating. To enable this, we develop a heat-budget-based scheduling system, called Sparta, which leverages dynamic voltage and frequency scaling (DVFS) to adaptively control CPU temperature. Sparta takes machine learning applications, datasets, and a temperature threshold as input. It sets the initial frequency of the CPU based on historical data and then dynamically updates it, according to the applications’ execution profile and ambient temperature, to safeguard edge devices. We find that for a suite of machine learning applications and deployment temperatures, Sparta is able to maintain CPU temperature below the threshold 94% of the time while facilitating improvements in execution time by 1.04x − 1.32x over competitive approaches. 

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4. Updated temperature correction for computing seawater nitrate with in situ ultraviolet spectrophotometer and submersible ultraviolet nitrate analyzer nitrate sensors

   https://doi.org/10.1002/lom3.10566  

   Plant, Joshua N.; Sakamoto, Carole M.; Johnson, Kenneth S.; Maurer, Tanya L.; Bif, Mariana B. (July 2023, Limnology and Oceanography: Methods)

   Abstract Sensors that use ultraviolet (UV) light absorption to measure nitrate in seawater at in situ temperatures require a correction to the calibration coefficients if the calibration and sample temperatures are not identical. This is mostly due to the bromide molecule, which absorbs more UV light as temperature increases. The current correction applied to in situ ultraviolet spectrophotometer (ISUS) and submersible ultraviolet nitrate analyzer (SUNA) nitrate sensors generally follows Sakamoto et al. (2009, Limnol. Oceanogr. Methods 7, 132–143). For waters warmer than the calibration temperature, this correction model can lead to a 1–2 μmol kg⁻¹positive bias in nitrate concentration. Here we present an updated correction model, which reduces this small but noticeable bias by at least 50%. This improved model is based on additional laboratory data and describes the temperature correction as an exponential function of wavelength and temperature difference from the calibration temperature. It is a better fit to the experimental data than the current model and the improvement is validated using two populations of nitrate profiles from Biogeochemical Argo floats navigating through tropical waters. One population is from floats equipped with ISUS sensors while the other arises from floats with SUNA sensors on board. Although this model can be applied to both ISUS and SUNA nitrate sensors, it should not be used for OPUS UV nitrate sensors at this time. This new approach is similar to that used for OPUS sensors (Nehir et al., 2021, Front. Mar. Sci. 8, 663800) with differing model coefficients. This difference suggests that there is an instrumental component to the temperature correction or that there are slight differences in experimental methodologies. 

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5. Efficient OpenCL Accelerators for Canny Edge Detection Algorithm on a CPU-FPGA Platform

   https://doi.org/10.1109/ReConFig48160.2019.8994769  

   Rahamneh, Samah; Sawalha, Lina (December 2019, International Conference on ReConFigurable Computing and FPGAs (ReConFig))

   The processing demands of current and emerging applications, such as image/video processing, are increasing due to the deluge of data, generated by mobile and edge devices. This raises challenges for a vast range of computing systems, starting from smart-phones and reaching cloud and data centers. Heterogeneous computing demonstrates its ability as an efficient computing model due to its capability to adapt to various workload requirements. Field programmable gate arrays (FPGAs) provide power and performance benefits and have been used in many application domains from embedded systems to the cloud. In this paper, we used a closely coupled CPU-FPGA heterogeneous system to accelerate a sliding window based image processing algorithm, Canny edge detector. We accelerated Canny using two different implementations: Code partitioned and data partitioned. In the data partitioned implementation, we proposed a weighted round-robin based algorithm that partitions input images and distributes the load between the CPU and the FPGA based on latency. The paper also compares the performance of the proposed accelerators with separate CPU and FPGA implementations. Using our hybrid CPU-FPGA based algorithm, we achieved a speedup of up to 4.8× over a CPU-only and up to 2.1× over a FPGA-only implementations. Moreover, the estimated total energy consumption of our algorithm is more efficient than a CPU-only implementation. Our results show a significant reduction in energy-delay product (EDP) compared to the CPU-only implementation, and comparable EDP results to the FPGA-only implementation. 

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