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Title: ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks
Recent algorithmic progression has brought competitive classification accuracy despite constraining neural networks to binary weights (+1/-1). These findings show remarkable optimization opportunities to eliminate the need for computationally-intensive multiplications, reducing memory access and storage. In this paper, we present ParaPIM architecture, which transforms current Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) sub-arrays to massively parallel computational units capable of running inferences for Binary-Weight Deep Neural Networks (BWNNs). ParaPIM's in-situ computing architecture can be leveraged to greatly reduce energy consumption dealing with convolutional layers, accelerate BWNNs inference, eliminate unnecessary off-chip accesses and provide ultra-high internal bandwidth. The device-to-architecture co-simulation results indicate ~4x higher energy efficiency and 7.3x speedup over recent processing-in-DRAM acceleration, or roughly 5x higher energy-efficiency and 20.5x speedup over recent ASIC approaches, while maintaining inference accuracy comparable to baseline designs.  more » « less
Award ID(s):
1740126
NSF-PAR ID:
10094200
Author(s) / Creator(s):
; ;
Date Published:
Journal Name:
24th Asia and South Pacific Design Automation Conference
Page Range / eLocation ID:
127 to 132
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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