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1. The Floquet Fluxonium Molecule: Driving Down Dephasing in Coupled Superconducting Qubits

   https://doi.org/10.1103/PRXQuantum.5.040314  

   Thibodeau, Matthew; Kou, Angela; Clark, Bryan K (October 2024, PRX Quantum)

   High-coherence qubits, which can store and manipulate quantum states for long times with low error rates, are necessary building blocks for quantum computers. Here we propose a driven superconducting erasure qubit, the Floquet fluxonium molecule, which minimizes bit-flip rates through disjoint support of its qubit states and suppresses phase flips by a novel second-order insensitivity to flux-noise dephasing. We estimate the bit-flip, phase-flip, and erasure rates through numerical simulations, with predicted coherence times of approximately 50 ms in the computational subspace and erasure lifetimes of about $500\text{μ}\mathrm{s}$. We also present a protocol for performing high-fidelity single-qubit rotation gates via additional flux modulation, on timescales of roughly 500 ns, and propose a scheme for erasure detection and logical readout. Our results demonstrate the utility of drives for building new qubits that can outperform their static counterparts. Published by the American Physical Society2024 

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2. Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study

   https://doi.org/10.1145/3650200.3656615  

   Oles, Vladyslav; Schmedding, Anna; Ostrouchov, George; Shin, Woong; Smirni, Evgenia; Engelmann, Christian (May 2024, ACM)

   GPU memory corruption and in particular double-bit errors (DBEs) remain one of the least understood aspects of HPC system reliability. Albeit rare, their occurrences always lead to job termination and can potentially cost thousands of node-hours, either from wasted com- putations or as the overhead from regular checkpointing needed to minimize the losses. As supercomputers and their components simultaneously grow in scale, density, failure rates, and environ- mental footprint, the eciency of HPC operations becomes both an imperative and a challenge. We examine DBEs using system telemetry data and logs col- lected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). Using exploratory data analysis and statistical learning, we extract several insights about memory reliability in such GPUs. We nd that GPUs with prior DBE occurrences are prone to experience them again due to otherwise harmless factors, correlate this phenomenon with GPU placement, and suggest manufacturing variability as a factor. On the general population of GPUs, we link DBEs to short- and long-term high power consumption modes while finding no signifcant correlation with higher temperatures. We also show that the workload type can be a factor in memory’s propensity to corruption. 

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3. Design and Evaluation of a Spintronic In-Memory Processing Platform for Non-Volatile Data Encryption

   https://doi.org/10.1109/TCAD.2017.2774291  

   Angizi, Shaahin; He, Zhezhi; Bagherzadeh, Nader; Fan, Deliang (November 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)

   In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel 4-terminal spin Hall effect-driven domain wall motion devices that could be employed as both non-volatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy ~15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent non-volatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ Advanced Encryption Standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES Energy-Delay Product (EDP) can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively. 

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4. Reference-Counter Aware Deduplication in Erasure-Coded Distributed Storage System

   https://doi.org/10.1109/NAS.2018.8515697  

   Liu, Tong; He, Xubin; Alibhai, Shakeel; Wu, Chentao (October 2018, 2018 IEEE International Conference on Networking, Architecture and Storage (NAS))

   In modern distributed storage systems, space efficiency and system reliability are two major concerns. As a result, contemporary storage systems often employ data deduplication and erasure coding to reduce the storage overhead and provide fault tolerance, respectively. However, little work has been done to explore the relationship between these two techniques. In this paper, we propose Reference-counter Aware Deduplication (RAD), which employs the features of deduplication into erasure coding to improve garbage collection performance when deletion occurs. RAD wisely encodes the data according to the reference counter, which is provided by the deduplication level and thus reduces the encoding overhead when garbage collection is conducted. Further, since the reference counter also represents the reliability levels of the data chunks, we additionally made some effort to explore the trade-offs between storage overhead and reliability level among different erasure codes. The experiment results show that RAD can effectively improve the GC performance by up to 24.8% and the reliability analysis shows that, with certain data features, RAD can provide both better reliability and better storage efficiency compared to the traditional Round- Robin placement. 

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5. Computationally Efficient Codes for Adversarial Binary-Erasure Channels

   https://doi.org/10.1109/ISIT54713.2023.10206731  

   Li, Sijie; Krishnan, Prasad; Jaggi, Sidharth; Langberg, Michael; Sarwate, Anand D. (June 2023, IEEE)

   We study communication models for channels with erasures in which the erasure pattern can be controlled by an adversary with partial knowledge of the transmitted codeword. In particular, we design block codes for channels with binary inputs with an adversary who can erase a fraction p of the transmitted bits. We consider causal adversaries, who must choose to erase an input bit using knowledge of that bit and previously transmitted bits, and myopic adversaries, who can choose an erasure pattern based on observing the transmitted codeword through a binary erasure channel with random erasures. For both settings we design efficient (polynomial time) encoding and decoding algorithms that use randomization at the encoder only. Our constructions achieve capacity for the causal and “sufficiently myopic” models. For the “insufficiently myopic” adversary, the capacity is unknown, but existing converses show the capacity is zero for a range of parameters. For all parameters outside of that range, our construction achieves positive rates. 

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