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1. Exploring the practical efficiency limit of silicon solar cells using thin solar-grade substrates

   https://doi.org/10.1039/d0ta04575f  

   Augusto, A.; Karas, J.; Balaji, P.; Bowden, S. G.; King, R. R. (August 2020, Journal of Materials Chemistry A)

   null (Ed.)

   Multiple silicon solar cell technologies have surpassed or are close to surpassing 26% efficiency. Dielectric and amorphous silicon-based passivation layers combined with minimal metal/silicon contact areas were responsible for reducing the surface saturation current density below 3 fA cm −2 . At open-circuit, in passivated contact solar cells, the recombination is mainly from fundamental mechanisms (Auger and radiative) representing over 3/4 of the total recombination. At the maximum power point, the fundamental recombination fraction can drop to half, as surface and bulk Shockley–Read–Hall step in. As a result, to further increase the performance at the operating point, it is paramount to reduce the bulk dependence and secure proper surface passivation. Bulk recombination can be mitigated either by reducing bulk defect density or by reducing the wafer thickness. We demonstrate that for commercially-viable solar-grade silicon, thinner wafers and surface saturation current densities below 1 fA cm −2 , are required to significantly increase the practical efficiency limit of solar cells up to 0.6% absolute. For a high-quality n-type bulk silicon minority-carrier lifetime of 10 ms, the optimum wafer thickness range is 40–60 μm, a very different value from 110 μm previously calculated assuming undoped substrates and solely Auger and radiative recombination. In this thickness range surface saturation current densities near 0.1 fA cm −2 are required to narrow the gap towards the fundamental efficiency limit. We experimentally demonstrate surface saturation currents below 0.5 fA cm −2 on pi/CZ/in structures across different wafer thicknesses (35–170 μm), with potential to reach open-circuit voltages close to 770 mV and bandgap-voltage offsets near 350 mV. Finally, we use the bandgap-voltage offset as a metric to compare the quality of champion experimental solar cells in the literature, for the most commercially-relevant photovoltaic cell absorbers and architectures. 

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2. Doping CdSe _x Te _1-x /CdTe Graded Absorber Films with Arsenic for Thin-Film Photovoltaics

   https://doi.org/10.1109/PVSC40753.2019.8981239  

   Munshi, Amit H.; Guo, Jinglong; Klie, Robert; Sampath, Walajabad S.; Danielson, Adam H.; Swain, Santosh; Reich, Carey L.; Shimpi, Tushar M.; McPherson, Seth W.; Lynn, Kelvin G.; et al (June 2019, 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC))

   CdTe thin-film photovoltaics have demonstrated some of the lowest costs of electricity generation owing to its low material cost and ease of manufacturing. However, the full potential of polycrystalline CdTe photovoltaics can only be realized if the open-circuit voltage can be increased beyond 1 V Open-circuit voltage ~850-900 mV has been consistently observed for state-of-the-art polycrystalline CdTe solar cells. Open-circuit voltage of over 1V has been demonstrated for single crystal CdTe devices by doping with Group V elements. Therefore, this study is aimed at understanding behavior of polycrystalline CdTe devices with arsenic doping, its activation and process and performance optimization in order to overcome current voltage limitations in CdTe solar cells. 

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3. Studying edge losses in silicon heterojunction solar cells

   https://doi.org/10.1109/PVSC45281.2020.9300984  

   Balaji, Pradeep; Bowden, Stuart; Augusto, Andre (June 2020, 2020 47th IEEE Photovoltaic Specialists Conference (PVSC))

   null (Ed.)

   In this manuscript we study the impact of edge losses in silicon heterojunction solar cells. The edge of the cells may play a larger role due to the large diffusion length of the carriers and the presence of a high conductive layer in this type of architecture. We fabricate silicon heterojunction solar cells with different areas and masking schemes to evaluate the impact of the edge on the open-circuit voltage. We measured lower open-circuit voltages on cells which have larger ratio of cell perimeter-to-area but have similar lifetimes and similar implied characteristics. The solar cell with 6 cm^2 shows open-circuit voltage 7 mV lower than the cell with 150.3 cm^2 . Electroluminescence and photoluminescence imaging are used to evaluate the diffusion of carriers at the edges of the cells. We show the out diffusion of carriers at the edges of the cell which demonstrates the cell is affected by the surroundings 

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4. Degradation of polycrystalline Si solar cell efficiency with increased incident optical power — Experiments and theory

   https://doi.org/10.1109/PVSC.2016.7750064  

   Connell, Ezra; Semichaevsky, Andrey (June 2016, 43rd IEEE-PVSC (Photovoltaic Specialists Conference), 2016)

   In this paper we discuss our experimental data obtained for several Si PV cell samples. From the I-V curves measured under various optical irradiance levels, we extracted the fill factors and the series and shunt resistances of the solar cells. For some of our samples, the solar cell efficiencies decrease even at illuminating power densities less than 1 Sun due to reductions in fill factors. Theoretical analysis suggests the reason for the observed dependences of PV cell circuit parameters on optical injection can be defect-mediated carrier recombination. 

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5. Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage

   https://doi.org/10.1109/IRPS48227.2022.9764569  

   Zhang, R.; Liu, J.; Li, Q.; Pidaparthi, S.; Edwards, A.; Drowley, C.; Zhang, Y. (March 2022, Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage)

   GaN high-electron-mobility transistors (HEMTs) are known to have no avalanche capability and insufficient short-circuit robustness. Recently, breakthrough avalanche and short-circuit capabilities have been experimentally demonstrated in a vertical GaN fin-channel junction-gate field-effect transistor (Fin-JFET), which shows a good promise for using GaN devices in automotive powertrains and electric grids. In particular, GaN Fin-JFETs demonstrated good short-circuit capability at avalanche breakdown voltage (BV AVA ), with a failure-to-open-circuit (FTO) signature. This work presents a comprehensive device physics-based study of the GaN Fin-JFET under short-circuit conditions, particularly at a bus voltage close to BV AVA . Mixed-mode electrothermal TCAD simulations were performed to understand the carrier dynamics, electric field distributions, and temperature profiles in the Fin-JFET under short-circuit and avalanche conditions. The results provide important physical references to understand the unique robustness of the vertical GaN Fin-JFET under the concurrence of short-circuit and avalanche as well as its desirable FTO signature. 

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