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1. A 120-330V, sub-μA, 4-Channel Driver for Microrobotic Actuators with Wireless-Optical Power Delivery and over 99% Current Efficiency

   https://doi.org/10.1109/VLSICircuits18222.2020.9162908  

   Rentmeister, J. S.; Pister, K.; Stauth, J. T. (July 2020, IEEE Symposium on VLSI Circuits (VLSI))

   This work presents a 4-channel, mm-scale, electrostatic and piezoelectric actuator driver that uses < 1μA total quiescent bias current and can drive actuator loads up to 120-330V at frequencies over 1kHz. The driver achieves over 99% current efficiency and can operate untethered with an integrated photovoltaic array driven by a collimated or diffuse optical power source. The circuit is tested with an off-chip boost circuit, generating over 1.5kV with 85% power efficiency at 45mW load. The system uses a simple 4-bit CMOS logic level interface with 100 kHz clock to actuate high voltage channels; on-chip photovoltaics also power the digital controller, and I/O bus. 

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2. Semi-Implantable Wireless Power Transfer (WPT) System Integrated With On-Chip Power Management Unit (PMU) for Neuromodulation Application

   https://doi.org/10.1109/JERM.2023.3256705  

   Biswas, Dipon K.; Saha, Nabanita; Kaul, Arnav; Mahbub, Ifana (June 2023, IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology)

   Miniaturization of the neuromodulation system is important for non-invasive or sub-invasive optogenetic application. This work presents an optimized wireless power transfer (WPT) system integrated with an on-chip rectification circuitry and an off-chip stimulation circuitry for optogenetic stimulation of freely moving rodents. The proposed WPT system is built using parallel transmitter (TX) coils on printed circuit board (PCB) and wire-wound based receiver (RX) coil followed by a seven-stage voltage doubler and a low dropout regulator (LDO) circuit designed in 180 nm standard Complementary Metal Oxide Semiconductor (CMOS) process. A pulse stimulation is used to stimulate the neurons which is generated using a commercially available off-the-shelf (COTS) components based oscillator circuit. The intensity of the stimulation is controlled by using a COTS based LED driver circuit which controls the current through the μ LED. The total dimension of the RX coil is 8 mm × 3.4 mm. The maximum power transfer efficiency (PTE) of the proposed WPT system is ∼ 35% and the power conversion efficiency (PCE) of the rectifier is 52%. The proposed system with reconfigurable stimulation frequency is suitable for exciting different brain areas for long-term health monitoring. 

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3. A Novel Energy-Efficient Sinusoidal Power Clocking-Based Writing Circuitry for the Hybrid CMOS/MTJ Architecture

   https://doi.org/10.1109/TMAG.2024.3430120  

   Yang, Wu; Degada, Amit; Thapliyal, Himanshu (September 2024, IEEE Transactions on Magnetics)

   Spin transfer torque magnetic random access memory (STT-MRAM) offers a promising solution for low-power and high-density memory due to its compatibility with CMOS, higher density, scalable nature, and non-volatility. However, the higher energy required to write bit cells has remained a key challenge for its adaptation into battery-operated smart handheld devices. The existing low-energy writing solutions require additional complex control logic mechanisms, further constraining the available area. In this research, we propose a solution to design energy-efficient write circuits by incorporating two techniques together. First, we propose the sinusoidal power clocking mechanism replacing the DC power supply in the conventional CMOS design. Second, we propose three lookup table (LUT)-based control logic circuits and one write circuit to reduce the area and further minimize energy dissipation. The experimental results are verified over the case study implementations of 4×4 STT-MRAM macro designed using bit cell configurations: i) one transistor and one magnetic tunnel junction (MTJ) (1T-1MTJ) and ii) four transistors and two MTJs (4T-2MTJ). The post-layout simulation for the frequency range from 250 kHz to 6.25 MHz shows that the write circuit, which uses the proposed LUT-based control logic circuits and a write driver with a sinusoidal power supply, achieves more than a 65.05% average energy saving compared to the CMOS counterpart. Furthermore, the write circuit, which uses the proposed 6T write driver with the sinusoidal power supply, shows an improvement in energy saving by more than 70.60% compared to the CMOS counterpart. We also verified that the energy-saving performance remains relatively consistent with the change in temperature and the tunneling magnetoresistance (TMR) ratio. 

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4. Compact ultra low power class AB buffer amplifier

   https://doi.org/10.1109/ROPEC.2017.8261576  

   Far, Ali (November 2017, IEEE)

   Targeting the energy harvesting applications that require multiple channels of matched buffer amplifiers on a chip, a small rail-to-rail input-output, ultra low current, and low supply voltage (VDD) buffer amplifier is presented. The contributions of this work are as follows: First, an output buffer driver utilizes a loser-take-all circuit (LTA) and a current mirror amplifier (CMA) circuit to regulate the current in either of the inactive sink or source output driver transistors (FET). In conjunction with the LTA and CMA, a complementary noninverting current mirror (CNICM), monitors and rectifies the sink-source output signals before they are fed to the LTA circuit. Hence, the amplifier's current consumption, attributed to monitoring external loads, is substantially curbed. More importantly, because all the elements of the buffer driver (LTA, CMA, and CNICM) operate mainly in current mode, the output buffer driver is structurally fast and can operate with low V DD of about V GS +2V DS . Second, a floating current source (FCS) function is emulated that can also operate with low VDD and is fast in lieu of utilizing auxiliary common gate amplifiers (CGA). The FCS contains two complementary cascoded FET current sources where the middle cascoded FET's VGSs are held constant and their drain currents are criss-crossed and fed to each other's source terminals, while CGAs regulate the V GS s of the lower FETs, whose currents are substantially equalized and mirrored into the Amplifier's bias network. Montecarlo (MC) and worst case (WC) simulations indicate the following specifications are achievable: V DD minimum ∼ 0.8v; I DD ∼ 200nA; input voltage range rail to rail; output voltage range ∼ 10mV from the rails; open loop gain (A V ) ∼ 115dB with unity gain bandwidth (f U ) ∼ 600KHz and phase margin (PM) ∼ 30 degrees; power supply rejection ratio (PSRR) ∼ − 88dB; common mode rejection ratio (CMRR) ∼ − 120dB; slew rate (SR) ∼ 2V/ 5uS; settling time (t S ) ∼ 10uS; output resistor (R L ) capability ∼10K Ohms; and die size rough estimate is 100 um per side. 

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5. Fine-Grained Energy Efficiency Using Per-Core DVFS with an Adaptive Runtime System

   https://doi.org/10.1109/IGSC48788.2019.8957174  

   Acun, Bilge; Chandrasekar, Kavitha; and Kale, Laxmikant (October 2020, International Green and Sustainable Computing Conference)

   Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce the power and/or energy consumption of various applications. While most processors provide chip-level DVFS, where the frequency and voltage of the cores in a chip can only be changed all together; core-level DVFS, where each core can be controlled independently, requires core-level voltage regulators in hardware and only is supported in production in Haswell generation among Intel processors. The finer grained control that per-core DVFS provides can lead to higher energy efficiency compared to chip-level DVFS especially for the unsynchronized, unstructured parallel applications when carefully applied. Ability to do per-core DVFS opens up new doors for different optimizations within runtime systems. We implement an intelligent energy efficient runtime module which uses a fine-grained function level per-core DVFS approach. Our module finds the energy-optimal frequency for each phase/function/kernel of the application over the first few iterations and applies the optimal frequency for each function. We test our implementation on Haswell processors and show that our algorithm enables 4% to 35% energy reduction over chip-level DVFS with as much as performance. 

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