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1. Auger effect limited performance in tunnel field effect transistors

   https://doi.org/10.1109/E3S.2017.8246156  

   Ahmed, Sheikh; Tan, Yaohua; Truesdell, Daniel; Ghosh, Avik (October 2017, 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S))

   null (Ed.)

   Tunnel field-effect-transistors (TFETs) are promising candidates for next generation transistors for low power applications, as the TFETs promise low subthreshold swing (SS). Different from traditional MOSFET, the TFETs rely on energy-efficient switching of band-to-band tunneling (BTBT), therefore the SS in TFETs is not limited by the 60 mV/decade Boltzmann limit. This reduction in energy consumption makes TFETs suitable candidates to replace standard MOSFETs in low power applications. However, most experimentally demonstrated TFETs suffer from low on current[1], and the theoretical low SS is compromised by impurities and Auger generation. To understand the underlying physics and predict the device characteristics of TFETs, sophisticated numerical simulations can be used. On the other hand, physics based compact models are also required to provide fast predictions for existing and new device concepts. Furthermore, a physics based compact model is more efficient to model the effects like Auger generation which could be time-consuming for numerical calculations. In this work, we introduce a physics based compact model for homojunction TFETs with Auger generation effect considered. This compact model is based on the modified Simmons' equation at finite temperature[2]. With our compact model, the possible impact of Auger generation effect to off-current and SS is explored. 

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2. A comprehensive analysis of Auger generation impacted planar Tunnel FETs

   https://doi.org/10.1016/j.sse.2020.107782  

   Ahmed, S. Z.; Truesdell, D. S.; Tan, Y.; Calhoun, B. H.; Ghosh, A. W. (March 2020, Solidstate electronics)

   null (Ed.)

   Tunnel Field Effect Transistors (TFETs) are known to be compromised by higher order processes that downgrade their performance compared to ballistic projections. Using a quasi-analytical model that extends the chemistry based Simmons equation to include finite temperature effects, potential variations and scattering, we exhibit that non-idealities like trap-assisted tunneling and Auger generation can explain the observed performance discrepancy. In particular, Auger generation is the dominant leakage mechanism in TFETs at low trap densities. Our studies suggest that possible ways of reducing Auger generation rate are reducing source carrier concentration and increasing the valence band transport effective mass of the source material. In this paper, we specifically investigate the impact of variations of these factors on device performance of staggered bandgap planar III-V heterojunction Tunnel FETs. 

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3. Towards Horizontal Heterojunctions for Tunnel Field Effect Transistors with Template Assisted Selective Epitaxy via MOCVD

   Brunelli, Simone; Markman, B; Wu, J; Tseng, HY; Goswami, A; Rodwell, M; Palmstrøm, P; Klamkin, K (June 2018, International conference on MOVPE)

   Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy. Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction. Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices. 

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4. TatC2 is Important for Growth of Acinetobacter baylyi Under Stress Conditions

   Langro, J. (October 2019, Fine focus)

   Protein export pathways are important for bacterial physiology among pathogens and non-pathogens alike. This includes the Twin-Arginine Translocation (Tat) pathway, which transports fully folded proteins across the bacterial cytoplasmic membrane. Some Tat substrates are virulence factors, while others are important for cellular processes like peptidoglycan remodeling. Some bacteria encode more than one copy of each Tat component, including the Gram-negative soil isolate Acinetobacter baylyi. One of these Tat pathways is essential for growth, while the other is not. We constructed a loss-of-function mutation to disrupt the non-essential tatC2 gene and assessed its contribution to cell growth under different environmental conditions. While the tatC2 mutant grew well under standard laboratory conditions, it displayed a growth defect and an aberrant cellular morphology when subjected to high temperature stress including an aberrant cellular morphology. Furthermore, increased sensitivities to detergent suggested a compromised cell envelope. Lastly, using an in vitro co-culture system, we demonstrate that the non-essential Tat pathway provides a growth advantage. The findings of this study establish the importance of the non-essential Tat pathway for optimal growth of A. baylyi in stressful environmental conditions. 

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5. Enhancing the graphene photocurrent using surface plasmons and a p-n junction

   https://doi.org/10.1038/s41377-020-00344-1  

   Wang, Di; Allcca, Andres E. Llacsahuanga; Chung, Ting-Fung; Kildishev, Alexander V.; Chen, Yong P.; Boltasseva, Alexandra; Shalaev, Vladimir M. (July 2020, Light: Science & Applications)

   Abstract The recently proposed concept of graphene photodetectors offers remarkable properties such as unprecedented compactness, ultrabroadband detection, and an ultrafast response speed. However, owing to the low optical absorption of pristine monolayer graphene, the intrinsically low responsivity of graphene photodetectors significantly hinders the development of practical devices. To address this issue, numerous efforts have thus far been made to enhance the light–graphene interaction using plasmonic structures. These approaches, however, can be significantly advanced by leveraging the other critical aspect of graphene photoresponsivity enhancement—electrical junction control. It has been reported that the dominant photocarrier generation mechanism in graphene is the photothermoelectric (PTE) effect. Thus, the two energy conversion mechanisms involved in the graphene photodetection process are light-to-heat and heat-to-electricity conversions. In this work, we propose a meticulously designed device architecture to simultaneously enhance the two conversion efficiencies. Specifically, a gap plasmon structure is used to absorb a major portion of the incident light to induce localized heating, and a pair of split gates is used to produce a p-n junction in graphene to augment the PTE current generation. The gap plasmon structure and the split gates are designed to share common key components so that the proposed device architecture concurrently realizes both optical and electrical enhancements. We experimentally demonstrate the dominance of the PTE effect in graphene photocurrent generation and observe a 25-fold increase in the generated photocurrent compared to the un-enhanced cases. While further photocurrent enhancement can be achieved by applying a DC bias, the proposed device concept shows vast potential for practical applications. 

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