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1. Role of transverse effective mass in Auger generation impacted planar III-V Tunnel FETs

   https://doi.org/10.1109/DRC46940.2019.9046439  

   Ahmed, Sheikh Z.; Tan, Yaohua; Ghosh, Avik W. (June 2019, 2019 Device Research Conference (DRC))

   null (Ed.)

   The Tunnel field-effect-transistor (TFET) has widely been considered as one of the most viable replacements to the complementary metal oxide semiconductor (CMOS) devices due to their superior theoretical performance. Practically, though there have been scant demonstrations of the sub-60mV/dec of TFETs 1 , it has yet to be realized at acceptable current levels over a substantial current swing needed for circuit operation. It is therefore imperative to study the primary delimiters of TFETs, mainly trap-assisted tunneling (TAT) and Auger generation 2-4 , along with ways to reduce them in order to improve device performance. The effect of TAT in TFETs has been studied extensively 3,4 . Here, we study the role of transverse effective mass on Auger generation in a planar TFET and propose a method of improving device performance. 

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2. Auger effect limited performance in tunnel field effect transistors

   https://doi.org/10.1109/E3S.2017.8246156  

   Ahmed, Sheikh; Tan, Yaohua; Truesdell, Daniel; Ghosh, Avik (October 2017, 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S))

   null (Ed.)

   Tunnel field-effect-transistors (TFETs) are promising candidates for next generation transistors for low power applications, as the TFETs promise low subthreshold swing (SS). Different from traditional MOSFET, the TFETs rely on energy-efficient switching of band-to-band tunneling (BTBT), therefore the SS in TFETs is not limited by the 60 mV/decade Boltzmann limit. This reduction in energy consumption makes TFETs suitable candidates to replace standard MOSFETs in low power applications. However, most experimentally demonstrated TFETs suffer from low on current[1], and the theoretical low SS is compromised by impurities and Auger generation. To understand the underlying physics and predict the device characteristics of TFETs, sophisticated numerical simulations can be used. On the other hand, physics based compact models are also required to provide fast predictions for existing and new device concepts. Furthermore, a physics based compact model is more efficient to model the effects like Auger generation which could be time-consuming for numerical calculations. In this work, we introduce a physics based compact model for homojunction TFETs with Auger generation effect considered. This compact model is based on the modified Simmons' equation at finite temperature[2]. With our compact model, the possible impact of Auger generation effect to off-current and SS is explored. 

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3. InP MOSFETs Exhibiting Record 70 mV/dec Subthreshold Swing

   Tseng, Hsin-Ying; Fang, Yihao; Zhong, Shibo; Rodwell, Mark (June 2019, 2019 IEEE Device Research Conference)

   Low InP/dielectric interface trap density Dit will enable low subthreshold swings (SS) in mm-wave MOSFETs [1] using InGaAs/InP composite channels [2] for increased breakdown and in tunnel FETs (TFETs) [3] using InAs/InP heterojunctions [4] for increased tunneling probability. Reducing Dit at the etched InP mesa edges of DHBTs and avalanche photodiodes will reduce leakage currents and increase breakdown voltages. While it can be difficult [5] to extract Dit of III-V interfaces from MOSCAP characteristics, Dit can be readily determined from the SS of long gate length Lg MOSFETs. Here we report InP-channel MOSFETs with record low SS indicating record low Dit at the semiconductor-dielectric interface. The devices use a AlOxNy/ZrO2 gate dielectric and a 14nm channel thickness Tch. A sample of 13 MOSFETs at 2 m Lg shows SS=70mV/dec. (mean) ±3 mV/dec. (standard deviation), corresponding to a minimum Dit ~3×1012 cm-2eV-1. The lowest SS observed at 2 m Lg is 66 mV/dec. The results suggest that wide-bandgap InP layers can be incorporated into MOS device designs without large degradations in DC characteristics arising from interface defects 

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4. Surface passivation extends single and biexciton lifetimes of InP quantum dots

   https://doi.org/10.1039/D0SC01039A  

   Yang, Wenxing; Yang, Yawei; Kaledin, Alexey L.; He, Sheng; Jin, Tao; McBride, James R.; Lian, Tianquan (June 2020, Chemical Science)

   Indium phosphide quantum dots (InP QDs) are nontoxic nanomaterials with potential applications in photocatalytic and optoelectronic fields. Post-synthetic treatments of InP QDs are known to be essential for improving their photoluminescence quantum efficiencies (PLQEs) and device performances, but the mechanisms remain poorly understood. Herein, by applying ultrafast transient absorption and photoluminescence spectroscopies, we systematically investigate the dynamics of photogenerated carriers in InP QDs and how they are affected by two common passivation methods: HF treatment and the growth of a heterostructure shell (ZnS in this study). The HF treatment is found to improve the PLQE up to 16–20% by removing an intrinsic fast hole trapping channel ( τ h,non = 3.4 ± 1 ns) in the untreated InP QDs while having little effect on the band-edge electron decay dynamics ( τ e = 26–32 ns). The growth of the ZnS shell, on the other hand, is shown to improve the PLQE up to 35–40% by passivating both electron and hole traps in InP QDs, resulting in both a long-lived band-edge electron ( τ e > 120 ns) and slower hole trapping lifetime ( τ h,non > 45 ns). Furthermore, both the untreated and the HF-treated InP QDs have short biexciton lifetimes ( τ xx ∼ 1.2 ± 0.2 ps). The growth of an ultra-thin ZnS shell (∼0.2 nm), on the other hand, can significantly extend the biexciton lifetime of InP QDs to 20 ± 2 ps, making it a passivation scheme that can improve both the single and multiple exciton lifetimes. Based on these results, we discuss the possible trap-assisted Auger processes in InP QDs, highlighting the particular importance of trap passivation for reducing the Auger recombination loss in InP QDs. 

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5. Towards Horizontal Heterojunctions for Tunnel Field Effect Transistors with Template Assisted Selective Epitaxy via MOCVD

   Brunelli, Simone; Markman, B; Wu, J; Tseng, HY; Goswami, A; Rodwell, M; Palmstrøm, P; Klamkin, K (June 2018, International conference on MOVPE)

   Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy. Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction. Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices. 

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