Title: Auger effect limited performance in tunnel field effect transistors
Tunnel field-effect-transistors (TFETs) are promising candidates for next generation transistors for low power applications, as the TFETs promise low subthreshold swing (SS). Different from traditional MOSFET, the TFETs rely on energy-efficient switching of band-to-band tunneling (BTBT), therefore the SS in TFETs is not limited by the 60 mV/decade Boltzmann limit. This reduction in energy consumption makes TFETs suitable candidates to replace standard MOSFETs in low power applications. However, most experimentally demonstrated TFETs suffer from low on current[1], and the theoretical low SS is compromised by impurities and Auger generation. To understand the underlying physics and predict the device characteristics of TFETs, sophisticated numerical simulations can be used. On the other hand, physics based compact models are also required to provide fast predictions for existing and new device concepts. Furthermore, a physics based compact model is more efficient to model the effects like Auger generation which could be time-consuming for numerical calculations. In this work, we introduce a physics based compact model for homojunction TFETs with Auger generation effect considered. This compact model is based on the modified Simmons' equation at finite temperature[2]. With our compact model, the possible impact of Auger generation effect to off-current and SS is explored. more »« less
Ahmed, S. Z.; Truesdell, D. S.; Tan, Y.; Calhoun, B. H.; Ghosh, A. W.
(, Solidstate electronics)
null
(Ed.)
Tunnel Field Effect Transistors (TFETs) are known to be compromised by higher order processes that downgrade their performance compared to ballistic projections. Using a quasi-analytical model that extends the chemistry based Simmons equation to include finite temperature effects, potential variations and scattering, we exhibit that non-idealities like trap-assisted tunneling and Auger generation can explain the observed performance discrepancy. In particular, Auger generation is the dominant leakage mechanism in TFETs at low trap densities. Our studies suggest that possible ways of reducing Auger generation rate are reducing source carrier concentration and increasing the valence band transport effective mass of the source material. In this paper, we specifically investigate the impact of variations of these factors on device performance of staggered bandgap planar III-V heterojunction Tunnel FETs.
Ahmed, Sheikh Z.; Tan, Yaohua; Ghosh, Avik W.
(, 2019 Device Research Conference (DRC))
null
(Ed.)
The Tunnel field-effect-transistor (TFET) has widely been considered as one of the most viable replacements to the complementary metal oxide semiconductor (CMOS) devices due to their superior theoretical performance. Practically, though there have been scant demonstrations of the sub-60mV/dec of TFETs 1 , it has yet to be realized at acceptable current levels over a substantial current swing needed for circuit operation. It is therefore imperative to study the primary delimiters of TFETs, mainly trap-assisted tunneling (TAT) and Auger generation 2-4 , along with ways to reduce them in order to improve device performance. The effect of TAT in TFETs has been studied extensively 3,4 . Here, we study the role of transverse effective mass on Auger generation in a planar TFET and propose a method of improving device performance.
Song, Jingfeng; Qi, Yubo; Xiao, Zhiyong; Wang, Kun; Li, Dawei; Kim, Seung-Hyun; Kingon, Angus I.; Rappe, Andrew M.; Hong, Xia
(, npj 2D Materials and Applications)
Abstract The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS2transistors back-gated by single-layer polycrystalline PbZr0.35Ti0.65O3. The devices exhibit current switching ratios up to 8 × 106within an ultra-low gate voltage window of$$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ V and subthreshold swing (SS) as low as 9.7 mV decade−1at room temperature, transcending the 60 mV decade−1Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.
Brunelli, Simone; Markman, B; Wu, J; Tseng, HY; Goswami, A; Rodwell, M; Palmstrøm, P; Klamkin, K
(, International conference on MOVPE)
Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy. Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction. Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices.
Abstract Probabilistic (p-) computing is a physics-based approach to addressing computational problems which are difficult to solve by conventional von Neumann computers. A key requirement for p-computing is the realization of fast, compact, and energy-efficient probabilistic bits. Stochastic magnetic tunnel junctions (MTJs) with low energy barriers, where the relative dwell time in each state is controlled by current, have been proposed as a candidate to implement p-bits. This approach presents challenges due to the need for precise control of a small energy barrier across large numbers of MTJs, and due to the need for an analog control signal. Here we demonstrate an alternative p-bit design based on perpendicular MTJs that uses the voltage-controlled magnetic anisotropy (VCMA) effect to create the random state of a p-bit on demand. The MTJs are stable (i.e. have large energy barriers) in the absence of voltage, and VCMA-induced dynamics are used to generate random numbers in less than 10 ns/bit. We then show a compact method of implementing p-bits by using VC-MTJs without a bias current. As a demonstration of the feasibility of the proposed p-bits and high quality of the generated random numbers, we solve up to 40 bit integer factorization problems using experimental bit-streams generated by VC-MTJs. Our proposal can impact the development of p-computers, both by supporting a fully spintronic implementation of a p-bit, and alternatively, by enabling true random number generation at low cost for ultralow-power and compact p-computers implemented in complementary metal-oxide semiconductor chips.
Ahmed, Sheikh, Tan, Yaohua, Truesdell, Daniel, and Ghosh, Avik.
"Auger effect limited performance in tunnel field effect transistors". 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S) (). Country unknown/Code not available. https://doi.org/10.1109/E3S.2017.8246156.https://par.nsf.gov/biblio/10207591.
@article{osti_10207591,
place = {Country unknown/Code not available},
title = {Auger effect limited performance in tunnel field effect transistors},
url = {https://par.nsf.gov/biblio/10207591},
DOI = {10.1109/E3S.2017.8246156},
abstractNote = {Tunnel field-effect-transistors (TFETs) are promising candidates for next generation transistors for low power applications, as the TFETs promise low subthreshold swing (SS). Different from traditional MOSFET, the TFETs rely on energy-efficient switching of band-to-band tunneling (BTBT), therefore the SS in TFETs is not limited by the 60 mV/decade Boltzmann limit. This reduction in energy consumption makes TFETs suitable candidates to replace standard MOSFETs in low power applications. However, most experimentally demonstrated TFETs suffer from low on current[1], and the theoretical low SS is compromised by impurities and Auger generation. To understand the underlying physics and predict the device characteristics of TFETs, sophisticated numerical simulations can be used. On the other hand, physics based compact models are also required to provide fast predictions for existing and new device concepts. Furthermore, a physics based compact model is more efficient to model the effects like Auger generation which could be time-consuming for numerical calculations. In this work, we introduce a physics based compact model for homojunction TFETs with Auger generation effect considered. This compact model is based on the modified Simmons' equation at finite temperature[2]. With our compact model, the possible impact of Auger generation effect to off-current and SS is explored.},
journal = {2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S)},
author = {Ahmed, Sheikh and Tan, Yaohua and Truesdell, Daniel and Ghosh, Avik},
editor = {null}
}
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