Internet of Things (IoT) devices have strict energy constraints as they often operate on a battery supply. The cryptographic operations within IoT devices consume substantial energy and are vulnerable to a class of hardware attacks known as side-channel attacks. To reduce the energy consumption and defend against side-channel attacks, we propose combining adiabatic logic and Magnetic Tunnel Junctions to form our novel Energy Efficient-Adiabatic CMOS/MTJ Logic (EE-ACML). EE-ACML is shown to be both low energy and secure when compared to existing CMOS/MTJ architectures. EE-ACML reduces dynamic energy consumption with adiabatic logic, while MTJs reduce the leakage power of a circuit. To show practical functionality and energy savings, we designed one round of PRESENT-80 with the proposed EE-ACML integrated with an adiabatic clock generator. The proposed EE-ACML-based PRESENT-80 showed energy savings of 67.24% at 25 MHz and 86.5% at 100 MHz when compared with a previously proposed CMOS/MTJ circuit. Furthermore, we performed a CPA attack on our proposed design, and the key was kept secret.
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Approximate Adiabatic Logic for Low-Power and Secure Edge Computing
Approximate computing is a promising approach for error-tolerant applications running on the Internet of Things (IoT) edge devices to reduce power consumption. However, approximate computation is susceptible to side-channel attacks, such as attacks based on differential power analysis (DPA). Energy efficiency could be further enhanced by applying adiabatic logic in approximate edge computing while increasing its protection against the side-channel attacks. As a case study, we are presenting two approximate adders based on adiabatic logic to illustrate the benefits of approximate computation combined with adiabatic logic. The proposed approximate adders leverage the dual-rail property of adiabatic logic to minimize the overall size and further decrease energy consumption. In this article, the first design is True Sum Approximate Adder (TSAA), while the second design is True Carry-out Approximate Adder (TCAA). There are fewer transistors in adiabatic logic-based TSAA and TCAA compared to CMOS based accurate mirror adder (AMA). At 12.5 MHz operating frequency and 45 nm technology node, the adiabatic TSAA and TCAA achieved power savings of 95.4% and 95.48%, energy savings of 90.80%, and 90.96% in comparison with the standard CMOS AMA. We also show that both designs proposed are more secure against DPA attacks.
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- Award ID(s):
- 1845448
- NSF-PAR ID:
- 10240281
- Date Published:
- Journal Name:
- IEEE Consumer Electronics Magazine
- ISSN:
- 2162-2248
- Page Range / eLocation ID:
- 1 to 1
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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The tremendous growth in the number of Internet of Things (IoT) devices has increased focus on the energy efficiency and security of an IoT device. In this paper, we will present a design level, non-volatile adiabatic architecture for low-energy and Correlation Power Analysis (CPA) resistant IoT devices. IoT devices constructed with CMOS integrated circuits suffer from high dynamic energy and leakage power. To solve this, we look at both adiabatic logic and STT-MTJs (Spin Transfer Torque Magnetic Tunnel Junctions) to reduce both dynamic energy and leakage power. Furthermore, CMOS integrated circuits suffer from side-channel leakage making them insecure against power analysis attacks. We again look to adiabatic logic to design secure circuits with uniform power consumption, thus, defending against power analysis attacks. We have developed a hybrid adiabatic-MTJ architecture using two-phase adiabatic logic. We show that hybrid adiabatic-MTJ circuits are both low energy and secure when compared with CMOS circuits. As a case study, we have constructed one round of PRESENT and have shown energy savings of 64.29% at a frequency of 25 MHz. Furthermore, we have performed a correlation power analysis attack on our proposed design and determined that the key was kept hidden.more » « less
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null (Ed.)Internet of Things (IoT) devices are mostly areas constrained and operate on a limited battery supply and therefore have tight energy budgets. Lightweight cryptography (LWC) such as PRESENT-80 allows for minimal area usage and low energy for secure operations. However, CMOS implemented LWCs are vulnerable to side-channel attacks such as Correlation Power Analysis (CPA). Adiabatic Logic is an emerging circuit design technique that can reduce energy consumption and be CPA resistant. Many existing adiabatic logic families use a 4-phase clocking scheme which pays a large area penalty. Thus, in this paper, we propose 2-EE-SPFAL, a 2-phase clocking scheme implementation of an existing adiabatic family known as EE-SPFAL. We explore 2-phase sinusoidal waves in terms of energy efficiency and security. To demonstrate energy savings and security against CPA attacks we construct one round of PRESENT-80 in both CMOS and 2-EE-SPFAL. Simulations were conducted using 45nm technology in Cadence Spectre. At 12.5MHz, our results show an average energy saving of 50% between CMOS and 2-EE-SPFAL. Furthermore, we performed a CPA attack on both the CMOS and 2-EE-SPFAL implementation and determined that the CMOS key could be retrieved while the adiabatic key was kept hidden.more » « less
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Charge-recycling adiabatic circuits are recently receiving increased attention due to both high energy-efficiency and higher resistance against side-channel attacks. These characteristics make adiabatic circuits a promising technique for Internet-of-things based applications. One of the important limitations of adiabatic logic is the higher intra-cell interconnect capacitance due to differential outputs and cross-coupled pMOS transistors. Since energy consumption has quadratic dependence on capacitance in adiabatic circuits (unlike conventional static CMOS where dependence is linear), higher interconnect capacitance significantly degrades the overall power savings that can be achieved by adiabatic logic, particularly in nanoscale technologies. In this paper, monolithic 3D integrated adiabatic circuits are introduced where transistor-level monolithic 3D technology is used to implement adiabatic gates. A 45 nm two-tier Mono3D PDK is used to demonstrate the proposed approach. Monolithic inter-tier vias are leveraged to significantly reduce parasitic interconnect capacitance, achieving up to 47% reduction in power-delay product as compared to 2D adiabatic circuits in a 45 nm technology node.more » « less
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null (Ed.)The adaptation of the Internet-of-Things (IoT) for consumer electronics has enabled us to uplift everyday life. Low-power smart and secure computing devices are needed to sustain the expected growth of consumer IoT. Adiabatic switching is a modern approach that recycles the energy stored in load capacitance to save energy. Further, the cryptographic circuit designed using adiabatic switching is secure against the Correlation Power Analysis (CPA) attack in contrast to the same circuit designed using standard CMOS. In this paper, we propose 2-SPGAL, a 2-phase sinusoidal signal based clocking implementation of Symmetric Pass Gate Adiabatic Logic (SPGAL). As a case study, we simulated the design of PRESENT-80 (a lightweight cryptographic scheme) one round with an in-built Power Clock Generator (PCG) with 45nm technology. The 2-SPGAL shows on an average 82.76% and 67.35% better energy saving compared to standard CMOS, and 2-EE-SPFAL (another 2-phase adiabatic logic), respectively at a frequency range from 100 kHz to 25 MHz with a load of 1 fF. The 2-SPGAL has 16.78% savings of the number of transistors compared to 2-EE-SPFAL for implementation of one round PRESENT-80. Further, the CPA attacks reveal the key in standard CMOS, however, 2-SPGAL PRESENT-80 adiabatic logic design was successful to protect the key.more » « less
- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1109/MCE.2021.3053908
