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1. Approximate Adiabatic Logic for Low-Power and Secure Edge Computing

   https://doi.org/10.1109/MCE.2021.3053908  

   Yang, Wu ; Thapliyal, Himanshu ( January 2021 , IEEE Consumer Electronics Magazine)

   Approximate computing is a promising approach for error-tolerant applications running on the Internet of Things (IoT) edge devices to reduce power consumption. However, approximate computation is susceptible to side-channel attacks, such as attacks based on differential power analysis (DPA). Energy efficiency could be further enhanced by applying adiabatic logic in approximate edge computing while increasing its protection against the side-channel attacks. As a case study, we are presenting two approximate adders based on adiabatic logic to illustrate the benefits of approximate computation combined with adiabatic logic. The proposed approximate adders leverage the dual-rail property of adiabatic logic to minimize the overall size and further decrease energy consumption. In this article, the first design is True Sum Approximate Adder (TSAA), while the second design is True Carry-out Approximate Adder (TCAA). There are fewer transistors in adiabatic logic-based TSAA and TCAA compared to CMOS based accurate mirror adder (AMA). At 12.5 MHz operating frequency and 45 nm technology node, the adiabatic TSAA and TCAA achieved power savings of 95.4% and 95.48%, energy savings of 90.80%, and 90.96% in comparison with the standard CMOS AMA. We also show that both designs proposed are more secure against DPA attacks.
2. 2-SPGAL: 2-Phase Symmetric Pass Gate Adiabatic Logic for Energy-Efficient Secure Consumer IoT

   https://doi.org/10.1109/ICCE50685.2021.9427720  

   Degada, Amit ; Thapliyal, Himanshu ( January 2021 , 2021 IEEE International Conference on Consumer Electronics (ICCE))

   The adaptation of the Internet-of-Things (IoT) for consumer electronics has enabled us to uplift everyday life. Low-power smart and secure computing devices are needed to sustain the expected growth of consumer IoT. Adiabatic switching is a modern approach that recycles the energy stored in load capacitance to save energy. Further, the cryptographic circuit designed using adiabatic switching is secure against the Correlation Power Analysis (CPA) attack in contrast to the same circuit designed using standard CMOS. In this paper, we propose 2-SPGAL, a 2-phase sinusoidal signal based clocking implementation of Symmetric Pass Gate Adiabatic Logic (SPGAL). As a case study, we simulated the design of PRESENT-80 (a lightweight cryptographic scheme) one round with an in-built Power Clock Generator (PCG) with 45nm technology. The 2-SPGAL shows on an average 82.76% and 67.35% better energy saving compared to standard CMOS, and 2-EE-SPFAL (another 2-phase adiabatic logic), respectively at a frequency range from 100 kHz to 25 MHz with a load of 1 fF. The 2-SPGAL has 16.78% savings of the number of transistors compared to 2-EE-SPFAL for implementation of one round PRESENT-80. Further, the CPA attacks reveal the key in standard CMOS, however, 2-SPGAL PRESENT-80 adiabatic logic design was successful to protectmore »the key.« less
3. Magnetic Interconnects Based on Composite Multiferroics

   https://doi.org/10.3390/mi13111991  

   Khitun, Alexander ( November 2022 , Micromachines)

   The development of magnetic logic devices dictates a need for a novel type of interconnect for magnetic signal transmission. Fast signal damping is one of the problems which drastically differs from conventional electric technology. Here, we describe a magnetic interconnect based on a composite multiferroic comprising piezoelectric and magnetostrictive materials. Internal signal amplification is the main reason for using multiferroic material, where a portion of energy can be transferred from electric to magnetic domains via stress-mediated coupling. The utilization of composite multiferroics consisting of piezoelectric and magnetostrictive materials offers flexibility for the separate adjustment of electric and magnetic characteristics. The structure of the proposed interconnect resembles a parallel plate capacitor filled with a piezoelectric, where one of the plates comprises a magnetoelastic material. An electric field applied across the plates of the capacitor produces stress, which, in turn, affects the magnetic properties of the magnetostrictive material. The charging of the capacitor from one edge results in the charge diffusion accompanied by the magnetization change in the magnetostrictive layer. This enables the amplitude of the magnetic signal to remain constant during the propagation. The operation of the proposed interconnects is illustrated by numerical modeling. The model is based on the Landau–Lifshitz–Gilbertmore »equation with the electric field-dependent anisotropy term included. A variety of magnetic logic devices and architectures can benefit from the proposed interconnects, as they provide reliable and low-energy-consuming data transmission. According to the estimates, the group velocity of magnetic signals may be up to 105 m/s with energy dissipation less than 10−18 J per bit per 100 nm. The physical limits and practical challenges of the proposed approach are also discussed.« less
4. High-Performance and Energy-Efficient 3D Manycore GPU Architecture for Accelerating Graph Analytics

   https://doi.org/10.1145/3482880  

   Choudhury, Dwaipayan ; Rajam, Aravind Sukumaran ; Kalyanaraman, Ananth ; Pande, Partha Pratim ( January 2022 , ACM Journal on Emerging Technologies in Computing Systems)

   Recent advances in GPU-based manycore accelerators provide the opportunity to efficiently process large-scale graphs on chip. However, real world graphs have a diverse range of topology and connectivity patterns (e.g., degree distributions) that make the design of input-agnostic hardware architectures a challenge. Network-on-Chip (NoC)- based architectures provide a way to overcome this challenge as the architectural topology can be used to approximately model the expected traffic patterns that emerge from graph application workloads. In this paper, we first study the mix of long- and short-range traffic patterns generated on-chip using graph workloads, and subsequently use the findings to adapt the design of an optimal NoC-based architecture. In particular, by leveraging emerging three-dimensional (3D) integration technology, we propose design of a small-world NoC (SWNoC)- enabled manycore GPU architecture, where the placement of the links connecting the streaming multiprocessors (SM) and the memory controllers (MC) follow a power-law distribution. The proposed 3D manycore GPU architecture outperforms the traditional planar (2D) counterparts in both performance and energy consumption. Moreover, by adopting a joint performance-thermal optimization strategy, we address the thermal concerns in a 3D design without noticeably compromising the achievable performance. The 3D integration technology is also leveraged to incorporate Near Data Processingmore »(NDP) to complement the performance benefits introduced by the SWNoC architecture. As graph applications are inherently memory intensive, off-chip data movement gives rise to latency and energy overheads in the presence of external DRAM. In conventional GPU architectures, as the main memory layer is not integrated with the logic, off-chip data movement negatively impacts overall performance and energy consumption. We demonstrate that NDP significantly reduces the overheads associated with such frequent and irregular memory accesses in graph-based applications. The proposed SWNoC-enabled NDP framework that integrates 3D memory (like Micron's HMC) with a massive number of GPU cores achieves 29.5% performance improvement and 30.03% less energy consumption on average compared to a conventional planar Mesh-based design with external DRAM.« less
5. RTD Light Emission around 1550 nm with IQE up to 6% at 300 K

   https://doi.org/10.1109/DRC50226.2020.9135175  

   Brown, E. R. ; Zhang, W-D. ; Fakhimi, P. ; Growden, T. A. ; Berger, P.R. ( June 2020 , IEEE Device Research Conference (DRC), Columbus, OH (June 22-24, 2020))

   Resonant tunneling diodes (RTDs) have come full-circle in the past 10 years after their demonstration in the early 1990s as the fastest room-temperature semiconductor oscillator, displaying experimental results up to 712 GHz and fmax values exceeding 1.0 THz [1]. Now the RTD is once again the preeminent electronic oscillator above 1.0 THz and is being implemented as a coherent source [2] and a self-oscillating mixer [3], amongst other applications. This paper concerns RTD electroluminescence – an effect that has been studied very little in the past 30+ years of RTD development, and not at room temperature. We present experiments and modeling of an n-type In0.53Ga0.47As/AlAs double-barrier RTD operating as a cross-gap light emitter at ~300K. The MBE-growth stack is shown in Fig. 1(a). A 15-μm-diam-mesa device was defined by standard planar processing including a top annular ohmic contact with a 5-μm-diam pinhole in the center to couple out enough of the internal emission for accurate free-space power measurements [4]. The emission spectra have the behavior displayed in Fig. 1(b), parameterized by bias voltage (VB). The long wavelength emission edge is at  = 1684 nm - close to the In0.53Ga0.47As bandgap energy of Ug ≈ 0.75 eV at 300 K.more »The spectral peaks for VB = 2.8 and 3.0 V both occur around  = 1550 nm (h = 0.75 eV), so blue-shifted relative to the peak of the “ideal”, bulk InGaAs emission spectrum shown in Fig. 1(b) [5]. These results are consistent with the model displayed in Fig. 1(c), whereby the broad emission peak is attributed to the radiative recombination between electrons accumulated on the emitter side, and holes generated on the emitter side by interband tunneling with current density Jinter. The blue-shifted main peak is attributed to the quantum-size effect on the emitter side, which creates a radiative recombination rate RN,2 comparable to the band-edge cross-gap rate RN,1. Further support for this model is provided by the shorter wavelength and weaker emission peak shown in Fig. 1(b) around = 1148 nm. Our quantum mechanical calculations attribute this to radiative recombination RR,3 in the RTD quantum well between the electron ground-state level E1,e, and the hole level E1,h. To further test the model and estimate quantum efficiencies, we conducted optical power measurements using a large-area Ge photodiode located ≈3 mm away from the RTD pinhole, and having spectral response between 800 and 1800 nm with a peak responsivity of ≈0.85 A/W at  =1550 nm. Simultaneous I-V and L-V plots were obtained and are plotted in Fig. 2(a) with positive bias on the top contact (emitter on the bottom). The I-V curve displays a pronounced NDR region having a current peak-to-valley current ratio of 10.7 (typical for In0.53Ga0.47As RTDs). The external quantum efficiency (EQE) was calculated from EQE = e∙IP/(∙IE∙h) where IP is the photodiode dc current and IE the RTD current. The plot of EQE is shown in Fig. 2(b) where we see a very rapid rise with VB, but a maximum value (at VB= 3.0 V) of only ≈2×10-5. To extract the internal quantum efficiency (IQE), we use the expression EQE= c ∙i ∙r ≡ c∙IQE where ci, and r are the optical-coupling, electrical-injection, and radiative recombination efficiencies, respectively [6]. Our separate optical calculations yield c≈3.4×10-4 (limited primarily by the small pinhole) from which we obtain the curve of IQE plotted in Fig. 2(b) (right-hand scale). The maximum value of IQE (again at VB = 3.0 V) is 6.0%. From the implicit definition of IQE in terms of i and r given above, and the fact that the recombination efficiency in In0.53Ga0.47As is likely limited by Auger scattering, this result for IQE suggests that i might be significantly high. To estimate i, we have used the experimental total current of Fig. 2(a), the Kane two-band model of interband tunneling [7] computed in conjunction with a solution to Poisson’s equation across the entire structure, and a rate-equation model of Auger recombination on the emitter side [6] assuming a free-electron density of 2×1018 cm3. We focus on the high-bias regime above VB = 2.5 V of Fig. 2(a) where most of the interband tunneling should occur in the depletion region on the collector side [Jinter,2 in Fig. 1(c)]. And because of the high-quality of the InGaAs/AlAs heterostructure (very few traps or deep levels), most of the holes should reach the emitter side by some combination of drift, diffusion, and tunneling through the valence-band double barriers (Type-I offset) between InGaAs and AlAs. The computed interband current density Jinter is shown in Fig. 3(a) along with the total current density Jtot. At the maximum Jinter (at VB=3.0 V) of 7.4×102 A/cm2, we get i = Jinter/Jtot = 0.18, which is surprisingly high considering there is no p-type doping in the device. When combined with the Auger-limited r of 0.41 and c ≈ 3.4×10-4, we find a model value of IQE = 7.4% in good agreement with experiment. This leads to the model values for EQE plotted in Fig. 2(b) - also in good agreement with experiment. Finally, we address the high Jinter and consider a possible universal nature of the light-emission mechanism. Fig. 3(b) shows the tunneling probability T according to the Kane two-band model in the three materials, In0.53Ga0.47As, GaAs, and GaN, following our observation of a similar electroluminescence mechanism in GaN/AlN RTDs (due to strong polarization field of wurtzite structures) [8]. The expression is Tinter = (2/9)∙exp[(-2 ∙Ug 2 ∙me)/(2h∙P∙E)], where Ug is the bandgap energy, P is the valence-to-conduction-band momentum matrix element, and E is the electric field. Values for the highest calculated internal E fields for the InGaAs and GaN are also shown, indicating that Tinter in those structures approaches values of ~10-5. As shown, a GaAs RTD would require an internal field of ~6×105 V/cm, which is rarely realized in standard GaAs RTDs, perhaps explaining why there have been few if any reports of room-temperature electroluminescence in the GaAs devices. [1] E.R. Brown,et al., Appl. Phys. Lett., vol. 58, 2291, 1991. [5] S. Sze, Physics of Semiconductor Devices, 2nd Ed. 12.2.1 (Wiley, 1981). [2] M. Feiginov et al., Appl. Phys. Lett., 99, 233506, 2011. [6] L. Coldren, Diode Lasers and Photonic Integrated Circuits, (Wiley, 1995). [3] Y. Nishida et al., Nature Sci. Reports, 9, 18125, 2019. [7] E.O. Kane, J. of Appl. Phy 32, 83 (1961). [4] P. Fakhimi, et al., 2019 DRC Conference Digest. [8] T. Growden, et al., Nature Light: Science & Applications 7, 17150 (2018). [5] S. Sze, Physics of Semiconductor Devices, 2nd Ed. 12.2.1 (Wiley, 1981). [6] L. Coldren, Diode Lasers and Photonic Integrated Circuits, (Wiley, 1995). [7] E.O. Kane, J. of Appl. Phy 32, 83 (1961). [8] T. Growden, et al., Nature Light: Science & Applications 7, 17150 (2018).« less