Due to its fast switching speed, the voltage sharing of series-connected SiC MOSFETs is more sensitive to the parasitic components from the power modules and the system, which results in more challenges for voltage balancing control. For two series-connected SiC MOSFETs realized by one half-bridge module, the detailed analysis and measurement indicate that the unbalanced parasitic capacitors inside the power module comprise the dominant factor causing the difference of turn-off dv/dt. In this paper, the traditional gate turn-off delay-time control is first used as an example to analyze the limitation of the existing active voltage balancing (AVB) control methods under AC load current: 1) AVB control has a limitation to adjust delay time accurately under AC current; 2) the voltage imbalance of the body diodes cannot be solved by AVB control. To achieve voltage balancing control of series-connected SiC MOSFETs and body diodes, this paper proposes a new two-part hybrid approach: 1) passive dv/dt compensation: one small compensation capacitor is applied to balance the non-uniform distribution of parasitic capacitors inside the power module, so the series-connected MOSFETs can have the same turn-off dv/dt; 2) active gate signal turn-off time adjustment: a closed-loop delay time control is applied to compensate the gate signal mismatch of MOSFETs. To verify the proposed balancing approach, a single-phase pump-back test is conducted to show the improvement of voltage sharing of both MOSFETs and body diodes.
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Space Charge Accumulation and Its Impact on High-Voltage Power Module Partial Discharge under DC and PWM Waves: Testing and Modeling
Emerging applications of compact high-voltage SiC modules pose strong challenges in the module package insulation design. Such SiC module insulations are subjected to both high voltage DC and PWM excitations between different terminals during different switching intervals. High dV/dt strongly interferes with partial discharge (PD) testing as it is hard to distinguish PD pulses and PWM excitation induced interferences. This paper covers both the testing and modeling of PD phenomena in high-voltage power modules. A high dV/dt PD testing platform is proposed, which involves a Super-High-Frequency (SHF, >3GHz) down-mixing PD detection receiver and a high-voltage scalable square wave generator. The proposed method captures SHF PD signatures and determines PDIV for packaging insulation. Using this platform, this paper provides a group of PDIV comparisons of packaging insulation under DC and PWM waveforms and discloses discrepancies in these PDIV results with respect to their excitations. Based on these PD testing results, the paper further provides a model using space charge accumulation to explain the PD difference under DC and PWM waveforms. Both simulation and sample testing results are included in this paper to support this hypothesis. With this new model, the paper includes an updated insulation design procedure for high-voltage power modules.
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- Award ID(s):
- 1846917
- NSF-PAR ID:
- 10241028
- Date Published:
- Journal Name:
- IEEE Transactions on Power Electronics
- ISSN:
- 0885-8993
- Page Range / eLocation ID:
- 1 to 1
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1109/TPEL.2021.3072655
