skip to main content
US FlagAn official website of the United States government
dot gov icon
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
https lock icon
Secure .gov websites use HTTPS
A lock ( lock ) or https:// means you've safely connected to the .gov website. Share sensitive information only on official, secure websites.


Title: Hybrid Voltage Balancing Approach for Series-Connected SiC MOSFETs for DC–AC Medium-Voltage Power Conversion Applications
Due to its fast switching speed, the voltage sharing of series-connected SiC MOSFETs is more sensitive to the parasitic components from the power modules and the system, which results in more challenges for voltage balancing control. For two series-connected SiC MOSFETs realized by one half-bridge module, the detailed analysis and measurement indicate that the unbalanced parasitic capacitors inside the power module comprise the dominant factor causing the difference of turn-off dv/dt. In this paper, the traditional gate turn-off delay-time control is first used as an example to analyze the limitation of the existing active voltage balancing (AVB) control methods under AC load current: 1) AVB control has a limitation to adjust delay time accurately under AC current; 2) the voltage imbalance of the body diodes cannot be solved by AVB control. To achieve voltage balancing control of series-connected SiC MOSFETs and body diodes, this paper proposes a new two-part hybrid approach: 1) passive dv/dt compensation: one small compensation capacitor is applied to balance the non-uniform distribution of parasitic capacitors inside the power module, so the series-connected MOSFETs can have the same turn-off dv/dt; 2) active gate signal turn-off time adjustment: a closed-loop delay time control is applied to compensate the gate signal mismatch of MOSFETs. To verify the proposed balancing approach, a single-phase pump-back test is conducted to show the improvement of voltage sharing of both MOSFETs and body diodes.  more » « less
Award ID(s):
2143488
PAR ID:
10500284
Author(s) / Creator(s):
; ; ;
Publisher / Repository:
IEEE
Date Published:
Journal Name:
IEEE Transactions on Power Electronics
Volume:
37
Issue:
7
ISSN:
0885-8993
Page Range / eLocation ID:
8104 to 8117
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. Abstract—Wide band gap (WBG) devices, like silicon carbide (SiC) MOSFET has gradually replaced the traditional silicon counterpart due to their advantages of high operating temperature and fast switching speed. Paralleling operations of SiC MOSFETs are unavoidable in high power applications in order to meet the system current requirement. However, parasitics mismatches among different paralleling devices would cause current unbalance issues, which would reduce the system reliability and maximum current capability. Thus, to achieve current balancing operation, this paper proposes a solution of using multi-level active gate driver, where the dynamic current sharing during turn-on and turn-off processes are achieved by adjusting the delays, intermediate turn-on and turn-off voltages. The static current sharing is maintained by regulating the static turn-on gate voltage, where the on-state resistance mismatch between different devices can be compensated. A double pulse test setup with two different SiC MOSFETs is built to emulate the scenario of worst case application with large differences of threshold voltage and on-state resistance. The experimental results demonstrate that the proposed active gate driver can achieve both dynamic and static current sharing operations for SiC MOSFETs with paralleling operation. Moreover, the system control diagram is discussed. Simulation studies are conducted to achieve closed-loop control of the paralleled SiC MOSFETs with the aid of the active gate driver approach. 
    more » « less
  2. null (Ed.)
    Emerging applications of compact high-voltage SiC modules pose strong challenges in the module package insulation design. Such SiC module insulations are subjected to both high voltage DC and PWM excitations between different terminals during different switching intervals. High dV/dt strongly interferes with partial discharge (PD) testing as it is hard to distinguish PD pulses and PWM excitation induced interferences. This paper covers both the testing and modeling of PD phenomena in high-voltage power modules. A high dV/dt PD testing platform is proposed, which involves a Super-High-Frequency (SHF, >3GHz) down-mixing PD detection receiver and a high-voltage scalable square wave generator. The proposed method captures SHF PD signatures and determines PDIV for packaging insulation. Using this platform, this paper provides a group of PDIV comparisons of packaging insulation under DC and PWM waveforms and discloses discrepancies in these PDIV results with respect to their excitations. Based on these PD testing results, the paper further provides a model using space charge accumulation to explain the PD difference under DC and PWM waveforms. Both simulation and sample testing results are included in this paper to support this hypothesis. With this new model, the paper includes an updated insulation design procedure for high-voltage power modules. 
    more » « less
  3. null (Ed.)
    Driving solutions for power semiconductor devices are experiencing new challenges since the emerging wide bandgap power devices, such as silicon carbide (SiC), with superior performance become commercially available. Generally, high switching speed is desired due to the lower switching loss, yet high dv/dt and di/dt can result in elevated electromagnetic interference (EMI) emission, false-triggering, and other detrimental effects during switching transients. Active gate drivers (AGDs) have been proposed to balance the switching losses and the switching speed of each switching transient. The review of the in-existence AGD methodologies for SiC devices has not been reported yet. This review starts with the essence of the slew rate control and its significance. Then a comprehensive review categorizing the state-of-the-art AGD methodologies is presented. It is followed by a summary of the AGDs control and timing strategies. In this work, using AGD to reduce the EMI noise of a 10 kV SiC MOSFET system is reported. This work also highlights other capabilities of AGDs including reliability enhancement of power devices and rebalancing the mismatched electrical parameters of parallel- and series-connected devices. These application scenarios of AGDs are validated via simulation and experimental results. 
    more » « less
  4. This paper describes a study evaluating 1.2 kV SiC MOSFETs in modular multilevel cascaded H-bridge (CHB) threephase inverter for medium voltage ac grid applications. The main purpose of this topology is to remove the need of a bulk 60 Hz transformer that is normally used to step up the output signal of a voltage source inverter to the medium voltage level. Using SiC devices (1.2 kV ~ 6.5 kV SiC MOSFETs), with their high breakdown voltage, enables the system to meet and withstand the medium voltage stress, with a minimized number of cascaded modules. The SiC-based power electronics, when used in the presented topology, they significantly reduce the complexity usually faced when Si devices are used to meet the medium voltage level and the power scalability. The simulation and preliminary experimental results, on a low-voltage prototype, verifies the ninelevel CHB topology that is presented in this paper. 
    more » « less
  5. High-performance switching devices like SiC MOSFETs introduce high-frequency ringing and overvoltage transients at motor terminals, leading to uneven voltage distribution across windings. In SiC-driven motors, the first coil and initial turns experience significant overvoltage stress, increasing the risk of insulation degradation and inter-turn faults. This study proposes an analog circuit to mitigate overvoltage stress. The circuit detects high dv/dt in the first coil and adaptively inserts a ceramic capacitor via a GaN switch, forming a low-impedance path for high-frequency currents. This diverts part of the transient energy to the second coil, reducing stress on the first coil and promoting uniform voltage distribution. The GaN switch remains closed to sustain the high-frequency current path through the capacitor, adapting to different operating conditions and cable lengths. The circuit was prototyped and experimentally validated on a 2hp induction motor driven by a SiC inverter, demonstrating its effectiveness in mitigating overvoltage stress. This compact solution enhances the reliability of SiC-driven motor systems by addressing uneven high-frequency voltage distribution. 
    more » « less